3D Memory Source Structure for Higher Density Without Finer Patterning
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Solution Overview
Problem
Existing two-dimensional (2D) semiconductor devices face limitations in integration density due to the need for expensive equipment to form fine patterns, which restricts their further enhancement.
Innovation Solution
The development of three-dimensional (3D) semiconductor memory devices with a source structure comprising sequentially stacked first and second source conductive patterns, an electrode structure with vertically stacked electrodes, and a vertical semiconductor pattern that penetrates both structures, enhancing integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional (2D) or planar semiconductor devices are used, then manufacturing processes are relatively simple, but integration density is limited due to the need for expensive equipment to form fine patterns
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertical structures. Memory cells are arranged in three dimensions with vertical channel structures extending through multiple stacked layers, allowing integration density to increase without requiring proportionally finer pattern dimensions. This dimensional transition enables continued scaling while avoiding the need for increasingly expensive lithography equipment.
2Manufacturing precision
If three-dimensional (3D) semiconductor memory devices are developed, then integration density is improved, but device structure complexity increases
Solution Approach 1:
The three-dimensional memory device is segmented into multiple functional layers stacked vertically, including alternating layers of first and second semiconductor materials, insulating layers, and electrode structures. Each layer performs a specific function, and this modular segmentation allows for systematic fabrication processes while achieving high integration density through vertical stacking rather than lateral expansion.
Solution Approach 2:
The patent employs nested structures where vertical channel structures are formed within recesses of alternating semiconductor layers, which are themselves nested within insulating layers and electrode structures. This nested arrangement maximizes space utilization in the vertical dimension while maintaining manufacturability through sequential layer formation processes.
3Manufacturing precision
If fine patterns are formed in 2D devices, then integration density increases, but expensive apparatuses are required
Solution Approach 1:
Instead of continuing to reduce lateral pattern dimensions in 2D devices, the patent forms patterns with moderate dimensions and achieves higher integration density by stacking multiple layers vertically. This approach maintains ease of manufacture with existing lithography equipment while increasing capacity through the third dimension, avoiding the need for increasingly expensive apparatuses required for sub-10nm patterning.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.