3D Memory Source Layer Formation via Carrier Substrate Removal

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Solution Overview

Problem

Existing three-dimensional memory devices face challenges in supporting high-performance CMOS circuitry due to degradation from collateral thermal cycling and hydrogen diffusion, which affects the performance of support circuitry for vertical NAND strings.

Innovation Solution

The development of a semiconductor structure and method that involves forming a memory die with alternating insulating and conductive layers, where memory stack structures with vertical semiconductor channels and memory films are created, and a source layer is formed directly on the distal end of the channels after removing the carrier substrate, enabling improved electrical connections and reduced process complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a carrier substrate is used to support the memory die during fabrication, then mechanical stability and ease of manufacturing are improved, but the electrical connection performance and contact resistance to the vertical semiconductor channels deteriorate

Engineering Contradiction:

Improveease of manufactureVSAvoidelectrical connection performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The source layer is formed in advance during the fabrication process, before the carrier substrate is removed. This preliminary formation of the source layer ensures that the electrical connection structure is already in place and optimized, eliminating the need for additional processing steps after substrate removal and ensuring low contact resistance from the beginning

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The carrier substrate is completely removed after serving its temporary support function during fabrication. This extraction of the carrier substrate eliminates the intermediate layer that would otherwise impede direct electrical contact, allowing the source layer to form a direct, low-resistance connection with the vertical semiconductor channels

Inventive Principle:

Principle #2Taking out (Extraction)

2Reliability

If the carrier substrate is removed to improve electrical connections, then contact resistance is reduced, but the mechanical stability and structural support are worsened

Engineering Contradiction:

Improvecontact resistanceVSAvoidmechanical stability

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The source layer is formed as a complete, continuous structure before the carrier substrate is removed. This preliminary formation ensures that the source layer can immediately assume the mechanical support function, providing structural stability while enabling direct electrical contact with the vertical semiconductor channels once the substrate is removed

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The source layer undergoes parameter changes through doping and annealing processes that transform it from a simple conductive layer into a mechanically robust and electrically optimized structure. These parameter changes enable the source layer to simultaneously provide mechanical support and low-resistance electrical contact after carrier substrate removal

Inventive Principle:

Principle #35Parameter changes

3Manufacturing precision

If additional processing steps are added to form the source layer after substrate removal, then electrical connection precision is improved, but the manufacturing complexity and process time are worsened

Engineering Contradiction:

Improveelectrical connection precisionVSAvoidprocess complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The formation of the source layer is merged with the standard fabrication process flow, combining multiple functions (conductive layer formation, source region creation, and electrical connection establishment) into a single integrated process step. This merging eliminates the need for separate post-substrate-removal processing and achieves high electrical connection precision without adding manufacturing complexity

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The source layer is formed preliminarily during the main fabrication process, incorporating all necessary doping, patterning, and structural formation steps before the carrier substrate is removed. This preliminary action ensures that the electrical connection precision is optimized while avoiding additional processing steps that would increase manufacturing complexity

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11508711B2Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer

Publication Date: 2022.11.22 SANDISK TECHNOLOGIES LLC

AI summary

A memory die includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures extending through the alternating stack, and each of the memory stack structures includes a respective vertical semiconductor channel and a respective memory film, drain regions located at a first end of a respective one of the vertical semiconductor channels, and a source layer having a first surface and a second surface. The first surface is located at a second end of each of the vertical semiconductor channels, and a semiconductor wafer is not located over the second surface of the source layer.