3D Memory Source Layer Formation via Carrier Substrate Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during the manufacture of three-dimensional memory devices poses challenges for the performance of support circuitry in bonded three-dimensional memory devices, where conventional methods for forming source layers are complex and inefficient.
Innovation Solution
A semiconductor structure is formed with a memory die bonded to a logic die, featuring an alternating stack of insulating and conductive layers, with memory stack structures that include vertical semiconductor channels and memory films, a source layer connected to the distal ends of the channels, and a pass-through via structure extending through a dielectric material portion, allowing for direct exposure and conductive material deposition on the channel ends, simplifying the formation of a source layer and connection pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to form source layers in bonded three-dimensional memory devices, then the support circuitry can be implemented, but the process becomes complex and inefficient due to collateral thermal cycling and hydrogen diffusion affecting CMOS devices
Solution Approach 1:
The patent extracts the source layer formation process from the conventional complex manufacturing sequence by directly exposing the distal ends of vertical semiconductor channels through carrier substrate removal, eliminating the need for separate source layer deposition steps and reducing process complexity
Solution Approach 2:
The patent performs preliminary actions by forming pass-through via structures and positioning connection pads before final source layer formation, allowing for simplified subsequent processing steps and reducing overall manufacturing complexity
2Reliability
If the carrier substrate is removed to expose vertical semiconductor channel ends for source layer formation, then contact resistance is reduced, but the CMOS devices suffer from collateral thermal cycling and hydrogen diffusion
Solution Approach 1:
The patent performs preliminary bonding of the memory die to the logic die before removing the carrier substrate, ensuring that the memory die is mechanically supported and protected during the carrier removal process, thereby minimizing thermal cycling and hydrogen diffusion exposure to CMOS devices
Solution Approach 2:
The logic die serves as an intermediary support structure that replaces the carrier substrate after bonding, providing mechanical support to the memory die while protecting CMOS devices from harmful thermal and chemical effects during the carrier removal process
3Ease of operation
If pass-through via structures are formed extending through dielectric material, then connection pads can be directly accessed, but the manufacturing process becomes more complex
Solution Approach 1:
The pass-through via structures serve multiple functions: they provide mechanical support through the dielectric material, establish electrical connection paths to connection pads, and enable direct access for subsequent source layer formation, thereby simplifying overall manufacturing despite increased structural complexity
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A pass-through via structure vertically extends through a dielectric material portion that is adjacent to the alternating stack. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A backside bonding pad or bonding wire is formed to be electrically connected to the pass-through via structure.