3D Memory Source Contact Structure for Vertical NAND Source Tips
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently forming top source contacts to doped semiconductor source tips, which are crucial for enhancing performance and integration in vertical NAND strings.
Innovation Solution
A method involving the formation of a semiconductor structure with a pillar semiconductor source portion and a tubular semiconductor source portion having an inner cavity, followed by the deposition of a metallic source layer on the semiconductor source structure, which includes oxidizing surface portions of the semiconductor material to create a semiconductor oxide spacer structure and subsequently forming a memory opening fill structure with a vertical semiconductor channel and a drain region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional planar source contact structure is used, then the manufacturing process is simple, but the electrical contact efficiency and device performance are insufficient
Solution Approach 1:
The source contact structure transitions from a conventional planar (2D) configuration to a three-dimensional structure comprising a pillar portion and a tubular portion with an inner cavity. This dimensional evolution enables the contact structure to wrap around and establish multiple contact points with the doped semiconductor source tip, significantly improving electrical contact efficiency while managing the increased structural complexity through systematic design.
Solution Approach 2:
The tubular semiconductor source portion features an inner cavity that can accommodate the doped semiconductor source tip, creating a nested configuration where the contact structure envelops the active element. This nesting arrangement maximizes the contact interface area and ensures reliable electrical connection between the source contact and the source tip, directly addressing the electrical contact efficiency requirement.
2Reliability
If the semiconductor source structure uses a simple pillar shape, then the manufacturing process is easier, but the contact area with the doped source tip is insufficient
Solution Approach 1:
The semiconductor source structure is divided into two distinct segments: a pillar semiconductor source portion and a tubular semiconductor source portion. Each segment can be formed through separate fabrication processes, allowing for optimized manufacturing of each component while achieving the combined benefit of increased contact area. The pillar portion provides structural support and initial contact, while the tubular portion extends the contact interface.
Solution Approach 2:
The source contact structure employs composite semiconductor material configurations, where the pillar and tubular portions may utilize different doping profiles, material compositions, or crystalline structures optimized for their respective functions. This composite approach enables simultaneous optimization of mechanical stability (pillar) and electrical contact area (tubular), while the modular nature facilitates staged manufacturing processes.
3Reliability
If a top source contact structure is formed without an inner cavity, then the fabrication process is simpler, but the electrical signal pathway stability is reduced
Solution Approach 1:
The tubular semiconductor source portion incorporates an inner cavity designed to receive and securely position the doped semiconductor source tip. This nested configuration ensures stable mechanical alignment and consistent electrical contact, preventing signal pathway instability. The cavity acts as a receptacle that maintains precise spatial relationships between contact elements, directly enhancing signal pathway reliability.
Solution Approach 2:
The inner cavity of the tubular source portion is specifically engineered with localized properties optimized for electrical contact, such as enhanced doping concentration, adjusted geometry, or specialized material composition in the contact region. This local optimization ensures stable electrical signal transmission through the contact interface, while the rest of the structure maintains its structural integrity and manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient formation of a three-dimensional memory device with improved top source contacts, enhancing the performance and integration of vertical NAND strings by providing a stable and conductive pathway for electrical signals.
Implementation Method 1
oxidizing surface portions of the semiconductor material layer and the semiconductor substrate around a bottom portion of the memory opening, whereby a semiconductor oxide spacer structure is formed
Data Source
AI summary
An alternating stack of insulating layers and spacer material layers is formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. A memory opening is formed through the alternating stack. A memory material layer, a semiconductor source structure, a vertical semiconductor channel, a dielectric core, and a drain region are formed in the memory opening. Dopants in the semiconductor source structure are activated after formation of the drain region. Subsequently, the substrate and a bottom portion of the memory film are removed and a metallic source layer is formed on the semiconductor source structure.