3D Memory Source Wiring Layout Without Word-Line Contact Plugs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Interconnecting elements on a substrate with a memory cell array located at a high position above a substrate is challenging due to the difficulty in forming a thick metallic source line without being affected by annealing, which increases resistance and reduces integration density, and requires numerous contact plugs that obstruct further integration.
Innovation Solution
A semiconductor device design where a source wiring layer is positioned on the memory cell array, electrically connected to the source line, eliminating the need for contact plugs through word lines and allowing for a thicker metallic layer, thus reducing resistance and increasing integration density, and enabling easy connection to transistors via via-plugs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact plugs are formed through word lines to connect source line to substrate, then electrical connection is achieved, but integration density is reduced and resistance increases
Solution Approach 1:
The patent transitions from vertical connection (contact plugs through word lines) to lateral connection (source wiring layer extending from memory cell array to transistor). The source wiring layer is positioned in the same plane as the memory cell array, eliminating the need for vertical penetration through multiple layers and reducing integration complexity.
Solution Approach 2:
The patent extracts the source line connection function from the word line structure. Instead of forming contact plugs through word lines, the source wiring layer is separately formed to extend from the memory cell array to the transistor, separating the source connection function from the word line structure.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a substrate, a logic circuit provided on the substrate, and a memory cell array provided over the logic circuit that includes a plurality of electrode layers stacked on top of one another and a semiconductor layer provided over the plurality of electrode layers. The semiconductor device further includes a first plug and a second plug provided above the logic circuit and electrically connected to the logic circuit, a bonding pad provided on the first plug, and a metallic wiring layer provided on the memory cell array, electrically connected to the semiconductor layer, and electrically connected to the second plug.