3D Memory Structure Self-Aligned Double Patterning
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Solution Overview
Problem
The challenge lies in manufacturing 3D stacked semiconductor memory structures with smaller unit cells and excellent electrical properties while maintaining structural integrity, as thinner charge trapping multilayers and high aspect ratio patterns are prone to collapse during the manufacturing process, complicating design and increasing costs.
Innovation Solution
A self-aligned double-patterning process is employed, involving the formation of trenches, dielectric layers, and spacers to create robust, high-density conductive patterns, ensuring structural stability and preventing pattern collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the thickness of the charge trapping multilayer is reduced to achieve smaller unit cells, then the size of the memory device is reduced, but the charge retention capability deteriorates
Solution Approach 1:
The charge trapping multilayer is divided into multiple distinct layers (first charge trapping layer, second charge trapping layer, and optional third charge trapping layer) with different materials and trapping mechanisms. This segmentation allows each layer to contribute differently to charge retention, enabling sufficient total retention capability even when the overall multilayer thickness is reduced for smaller unit cells.
2Reliability
If double gate unit cells and surrounding gate unit cells are used to improve electrical performance, then the electrical properties are enhanced, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies different gate configurations to different regions or types of memory cells within the same device. Single-gate unit cells are used in regions where simpler structure is beneficial, while double-gate or surrounding-gate unit cells are used in regions where enhanced electrical performance is required. This local differentiation allows optimization of electrical properties without uniformly increasing device complexity across the entire structure.
3Volume of moving object
If thinner and higher patterns are fabricated to reduce dimensions, then the storage capacity is increased, but the patterns are prone to collapse during manufacturing
Solution Approach 1:
The patent employs a self-aligned double-patterning process where mandrel structures are first formed, then spacer structures are deposited and patterned in a subsequent step. This preliminary formation of mandrels provides structural support during the spacer formation process, preventing collapse of thin and high patterns. The self-alignment mechanism ensures precise positioning without requiring additional alignment steps that could compromise pattern stability.
Solution Approach 2:
Mandrel structures serve as intermediary elements that facilitate the formation of the final spacer patterns. These mandrels provide temporary structural support and define the positions of the spacers, enabling the creation of thin and high patterns that would otherwise be unstable during manufacturing. The mandrels are removed after serving their intermediary function, leaving the stable spacer structures.
4Ease of manufacture
If conventional patterning processes are used to manufacture 3D stacked structures, then the manufacturing process is simpler, but the manufacturing precision and yield are reduced due to pattern collapse
Solution Approach 1:
The self-aligned double-patterning process performs preliminary pattern formation using mandrels that self-align with subsequent spacer structures. This preliminary action establishes precise positional relationships between features without requiring complex alignment steps, thereby improving manufacturing precision while maintaining relative process simplicity through the self-aligned mechanism.
Data Source
AI summary
A method for manufacturing semiconductor device is disclosed. A substrate with a conductive layer is provided, and a dummy layer is formed on the conductive layer. The dummy layer and at least a portion of the conductive layer are patterned to form several trenches. A first dielectric layer is formed to fill into the trenches so as to form several first dielectric elements in the trenches. The dummy layer is removed to expose parts of the first dielectric elements. A second dielectric layer is formed on the exposed parts of the first dielectric elements, and the second dielectric layer is patterned so that a spacer is formed at a lateral side of each exposed first dielectric element. The conductive layer is patterned by the spacers, so that a patterned conductive portion is formed at each lateral side of each first dielectric element.