3D Memory Cell Layout With Split Channels and Conductive Pillars
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration density of electronic components increases, but this leads to challenges such as reduced feature sizes and complex manufacturing processes, necessitating innovative methods for forming memory devices with higher cell density and efficient interconnect structures.
Innovation Solution
The development of a 3D memory array with vertically stacked memory cells, utilizing a multi-layer stack of dielectric and sacrificial layers, where conductive pillars are formed to divide channel layers and charge storage layers, allowing for 2 bits/cell storage and higher cell density, and the use of interconnect structures to connect conductive pillars efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing complexity and process difficulty increase
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked architecture, where memory cells are arranged in multiple vertical layers. This dimensional change allows significantly higher integration density without proportionally increasing lateral feature size reduction, thereby mitigating manufacturing complexity while achieving greater component density.
Solution Approach 2:
The memory device is segmented into multiple functional layers including bit lines, word lines, charge storage layers, and channel layers stacked vertically. This segmentation allows each layer to be optimized independently and enables parallel processing during fabrication, reducing overall manufacturing complexity despite high integration density.
2Quantity of substance
If feature size is reduced to increase cell density, then storage capacity increases, but electrical isolation and signal integrity become more difficult to maintain
Solution Approach 1:
Dielectric layers are introduced as intermediary materials between adjacent conductive elements and memory cells. These dielectric layers provide electrical isolation and prevent signal interference, maintaining reliability even as feature sizes are reduced and cell density increases. The dielectric materials act as mediators that enable closer spacing while preserving electrical integrity.
3Ease of manufacture
If conventional planar memory structure is used, then manufacturing process is simpler, but storage density is limited
Solution Approach 1:
The patent employs vertical stacking of memory cells in three dimensions, creating multiple layers of bit lines, word lines, and charge storage regions stacked above the substrate. This 3D architecture achieves high storage density without requiring proportionally smaller feature sizes, maintaining manufacturing feasibility while dramatically increasing capacity.
Solution Approach 2:
Multiple functional layers are nested vertically, with each layer containing complete memory cell structures that include channel layers, charge storage layers, and interconnect structures. This nested arrangement maximizes space utilization and achieves high density while using standardized fabrication processes.
Data Source
AI summary
A memory device includes a first multi-layer stack, a channel layer, a charge storage layer, a first conductive pillar, and a second conductive pillar. The first multi-layer stack is disposed on a substrate and includes first conductive layers and first dielectric layers stacked alternately. The channel layer penetrates through the first conductive layers and the first dielectric layers, wherein the channel layer includes a first channel portion and a second channel portion separated from each other. The charge storage layer is disposed between the first conductive layers and the channel layer. The first conductive pillar is disposed between one end of the first channel portion and one end of the second channel portion. The second conductive pillar is disposed between the other end of the first channel portion and the other end of the second channel portion.