3D Semiconductor Memory Stack With Vertical Channels and Split Doping
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Solution Overview
Problem
Two-dimensional semiconductor devices face limitations in integration due to the need for expensive equipment to achieve finer patterns, which restricts their ability to increase storage capacity and performance while maintaining cost-effectiveness.
Innovation Solution
A three-dimensional semiconductor memory device is developed, featuring a stack structure with vertically oriented channel structures and a substrate with doped regions of different conductivity types, allowing for increased storage capacity per unit area and improved electrical characteristics by separating the peripheral circuit and cell array structures and using a staircase structure for the gate electrodes and interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration is limited by the area occupied by a unit memory cell and requires expensive process equipment to increase pattern fineness
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory structures. The memory cells are arranged in multiple layers with vertical channel structures penetrating through stacked gate electrodes and interlayer dielectric layers, enabling increased integration capacity without requiring proportionally finer pattern dimensions in the planar direction.
2Productivity
If pattern fineness is increased to improve integration, then storage capacity increases, but expensive process equipment is required
Solution Approach 1:
The invention achieves increased storage capacity by utilizing the vertical dimension through stacked memory cell layers and vertical channel structures, rather than relying solely on reducing planar pattern dimensions. This approach increases integration without requiring the same degree of expensive fine-patterning equipment.
Solution Approach 2:
The patent employs selective doping of the substrate with different conductivity types in different regions (first doped region with first conductivity type, second doped region with second conductivity type) to optimize electrical characteristics in specific areas, allowing for improved performance without requiring uniform high-precision processing throughout the entire device.
3Device complexity
If peripheral circuit structure and cell array structure are integrated on the same substrate, then device complexity is reduced, but peripheral transistors may be damaged during thermal processes
Solution Approach 1:
The patent divides the semiconductor device into distinct peripheral circuit region and cell array region on the substrate, with separate doping regions and contact structures for each. This segmentation allows different thermal processing conditions to be applied to each region, protecting peripheral transistors from damage while maintaining overall device integration.
Solution Approach 2:
The patent applies different doping characteristics to different regions: the peripheral circuit region has specific doped regions with conductivity types optimized for peripheral transistors, while the cell array region has doping configured for memory cell operation. This localized optimization protects peripheral transistors during thermal processes while maintaining device integration.
4Productivity
If three-dimensional vertically arranged memory cells are implemented, then storage capacity per unit area increases, but device structure becomes more complex
Solution Approach 1:
The patent implements three-dimensional memory cells with vertical channel structures that penetrate through multiple stacked layers of gate electrodes and interlayer dielectric materials. This vertical arrangement increases storage capacity per unit area by utilizing the third dimension while maintaining a systematic layered structure that manages complexity through regular repetition of structural units.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the electrical characteristics and reliability of the three-dimensional semiconductor memory device, enabling higher storage capacity and preventing damage to peripheral transistors during thermal processes, thus addressing the limitations of two-dimensional devices.
Implementation Method 1
The second substrate may include a first portion, a second portion, and a third portion. The first portion may be in contact with the first vertical channel structures and may be doped to have a first conductivity type. The second portion may be in contact with the second vertical channel structures and may be doped to have a second conductivity type different from the first conductivity type.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a first substrate including a cell array region and a cell array contact region, a peripheral circuit structure on the first substrate, and a cell array structure. The cell array structure may include a stack on the peripheral circuit structure, first vertical channel structures and second vertical channel structures on the cell array region and penetrating the stack, and a second substrate connected to the first vertical channel structures and second vertical channel structures. The stack may be between the peripheral circuit structure and the second substrate. The second substrate may include a first portion and a second portion. The first portion may contact the first vertical channel structures and may be doped a first conductivity type. The second portion may contact the second vertical channel structures and may be doped a second conductivity type different from the first conductivity type.