3D Memory Source Structure With Split Doping for Reliable Scaling
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Solution Overview
Problem
Existing two-dimensional semiconductor memory devices have limited capacity, while three-dimensional semiconductor memory devices face challenges in improving operation reliability and integration density.
Innovation Solution
A semiconductor memory device with a gate structure and source structure design that includes insulating and conductive layers alternately stacked, pillar structures penetrating these layers, and a doped semiconductor structure with varying dopant concentrations, enhancing integration and operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory cell array is used to increase capacity, then storage capacity is improved, but operation reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating different dopant concentrations in specific regions of the source structure. The first doped region has a first dopant concentration while the second doped region has a second dopant concentration, allowing different areas to serve different functional purposes - improving reliability in critical regions while maintaining high capacity in the overall three-dimensional structure
Solution Approach 2:
The patent changes the dopant concentration parameter within the source structure by creating regions with different dopant concentrations. This parameter variation allows optimization of electrical characteristics in different areas, improving operation reliability while maintaining the high-capacity three-dimensional architecture
2Quantity of substance
If three-dimensional memory cell array is used to increase capacity, then storage capacity is improved, but integration density deteriorates
Solution Approach 1:
The patent segments the source structure into multiple doped regions with different concentrations, allowing independent optimization of each segment. This segmentation enables better control over the complex three-dimensional structure, improving integration density while maintaining high storage capacity through the vertical stacking architecture
3Reliability
If doped semiconductor structure with varying dopant concentrations is used, then operation reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements local quality by introducing varying dopant concentrations only in specific regions of the source structure rather than throughout the entire device. This targeted approach improves operation reliability in critical areas while minimizing the increase in overall device complexity
Data Source
AI summary
A semiconductor memory device includes a pillar structure of a first row and a pillar structure of a second row, which penetrate a gate structure, extend to the inside of a source structure, and are adjacent to each other. The source structure includes a first semiconductor layer and a second semiconductor layer, which are stacked between the pillar structure of the first row and the pillar structure of the second row, or includes a first doped region and a second doped region, which have different concentrations of a conductivity type dopant between the pillar structure of the first row and the pillar structure of the second row.