3D Memory Array Layout With Split Control Logic Footprint
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Solution Overview
Problem
Microelectronic device designs face challenges in increasing memory density and performance due to processing conditions and the complexity of control logic devices, which often consume more space than memory devices, limiting the reduction of device size and improvement of performance metrics such as speed and power consumption.
Innovation Solution
The microelectronic device structure is designed with split control logic devices across multiple regions, allowing for a reduced horizontal footprint and increased memory density by vertically stacking memory cells and distributing control logic operations across distinct regions, including CMOS devices for enhanced control operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are integrated within a base control logic structure underlying the memory array, then control operations can be performed, but the control logic devices consume excessive real estate and limit memory density
Solution Approach 1:
The control logic devices are segmented into multiple independent assemblies (first control logic device assembly, second control logic device assembly, etc.) that can be separately formed and then integrated with the memory array. This segmentation allows each control logic assembly to be optimized independently and reduces the overall footprint by distributing control functions across multiple smaller units rather than requiring one large centralized control logic structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration of control logic devices to a three-dimensional architecture where control logic assemblies are stacked vertically above the memory array. This vertical stacking in the third dimension allows control logic devices to be integrated without increasing the horizontal footprint, effectively decoupling control functionality from area consumption.
2Productivity
If processing conditions are optimized for memory array formation, then memory device performance improves, but control logic device configurations and performance are limited
Solution Approach 1:
The control logic device assemblies are formed separately and completely before being integrated with the memory array. This preliminary formation allows the control logic devices to be manufactured under their own optimized processing conditions without being constrained by the memory array's processing requirements. The pre-formed assemblies are then transferred and integrated with the memory structure, decoupling the processing condition constraints.
Solution Approach 2:
By dividing the control logic devices into separate formable assemblies independent of the memory array, each assembly can be processed under conditions optimal for its specific requirements. This segmentation breaks the coupling between memory and control logic processing, allowing independent optimization of both components.
3Area of stationary object
If feature dimensions are reduced to increase integration density, then device compactness improves, but manufacturing precision requirements increase
Solution Approach 1:
The segmentation of control logic devices into separate assemblies allows each assembly to be formed with standard precision requirements, avoiding the need to reduce feature dimensions across the entire device. The modular approach maintains larger, more manufacturable feature sizes while achieving compact overall device footprint through vertical integration.
Solution Approach 2:
By moving control logic devices to a vertical stacking architecture, the patent achieves compactness in the horizontal plane without reducing feature dimensions. The third dimension provides the compression needed for high density while maintaining manufacturable feature sizes in the lateral dimensions.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure vertically neighboring the first microelectronic device structure. The first microelectronic device structure comprises a first memory array region and a first control logic device region and the second microelectronic device structure comprises a second memory array region and a first control logic device region. A third control logic device region vertically overlies the second microelectronic device structure. The first control logic device region includes sense amplifier devices for the first memory array region. The second control logic device region includes additional sense amplifier devices and sub word line drivers for the second memory array region. The third control logic device region includes additional sub word line drivers for the second memory array region. Related microelectronic devices, electronic systems, and methods are also described.