3D Memory Stack with Split Peripheral Circuits for Density Scaling
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Solution Overview
Problem
Planar memory cells face density limitations and scaling challenges due to feature size constraints, leading to increased costs and complexity in fabrication, while existing 3D memory architectures face issues with peripheral circuit area and voltage compatibility.
Innovation Solution
A 3D memory device architecture with DFM and NAND memory cell arrays stacked in different planes, utilizing capacitor-free multi-gate vertical 1T memory structures and separate peripheral circuits with varying operating voltages, fabricated on different substrates and bonded using hybrid or transfer bonding techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density is improved, but manufacturing precision and fabrication complexity worsen
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional stacked architecture. Multiple memory cell arrays are stacked vertically with peripheral circuits placed in separate tiers, enabling continued density improvement without further scaling lateral dimensions and avoiding the manufacturing precision challenges of sub-lithographic scaling
2Quantity of substance
If feature sizes of memory cells are reduced, then memory density is improved, but device complexity and fabrication cost increase
Solution Approach 1:
The memory device is segmented into multiple independent semiconductor structures (first memory cell array structure, second memory cell array structure, first peripheral circuit structure, second peripheral circuit structure) that are fabricated separately and then bonded together. This segmentation allows each structure to be optimized independently and simplifies the fabrication process for each component
3Quantity of substance
If 3D memory architecture is implemented, then memory density is improved, but peripheral circuit area increases
Solution Approach 1:
Peripheral circuits are moved from the planar domain to the vertical domain by stacking them in separate tiers above and below the memory cell arrays. The first peripheral circuit structure is positioned above the first memory cell array, and the second peripheral circuit structure is positioned below the second memory cell array, effectively utilizing the third dimension to accommodate peripheral circuits without increasing chip footprint
4Device complexity
If peripheral circuits are integrated with memory arrays, then device complexity is reduced, but voltage compatibility issues arise
Solution Approach 1:
The device is divided into separate semiconductor structures: memory cell arrays and peripheral circuits are fabricated on different substrates as independent structures. These structures are then bonded together through wafer-level bonding, allowing each structure to be optimized for its specific voltage requirements while maintaining electrical connectivity through the bonding interfaces
Solution Approach 2:
Different regions of the device have different voltage characteristics optimized for their specific functions. The first peripheral circuit structure operates at a first operating voltage, while the second peripheral circuit structure operates at a second operating voltage, allowing each region to be locally optimized for its operational requirements
Data Source
AI summary
Three-dimensional (3D) memory devices and fabricating methods are disclose. A disclosed 3D memory device can comprises, a first semiconductor structure comprising an array of first type memory cells, a second semiconductor structure comprising an array of second type memory cells different from the first type memory cells, a third semiconductor structure comprising a first peripheral circuit, and a fourth semiconductor structure comprising a second peripheral circuit. The first semiconductor structure and the second semiconductor structure are sandwiched between the third semiconductor structure and the fourth semiconductor structure in a vertical direction.