3D Memory Device With On-Die SRAM Buffering
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Solution Overview
Problem
Conventional 3D memory devices face challenges with poor array efficiency, large die size, high cost, and limited I/O speed due to peripheral circuits occupying significant space and thermal budget constraints, which hinder high-speed sequential programming and memory density.
Innovation Solution
Incorporating on-die static random-access memory (SRAM) cells on the same chip as peripheral circuits, allowing for high-speed read and write operations and enabling high-speed sequential programming without additional space requirements, and using SRAM as a cache or data buffer to optimize memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If peripheral circuits are integrated on the same chip as memory array, then device functionality is improved, but die size increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking, placing peripheral circuits and memory arrays in different vertical layers. This dimensional change allows both components to coexist on the same chip substrate without occupying excessive planar area, thus resolving the contradiction between functional integration and die size.
Solution Approach 2:
The patent implements a nested architecture where peripheral circuits are integrated within or alongside the memory array structure in the vertical dimension. The circuits are positioned in adjacent tiers or layers, allowing compact packaging of multiple functional elements within a small footprint, effectively reducing die size while maintaining full functionality.
2Quantity of substance
If conventional 3D memory architecture is used, then memory density is improved, but I/O speed is limited
Solution Approach 1:
The patent introduces an on-die buffer as an intermediary component between the host interface and the memory array. This buffer, implemented using SRAM cells, acts as a high-speed cache that temporarily stores data during read/write operations, thereby accelerating I/O speeds without compromising the high density achieved through 3D stacking.
Solution Approach 2:
The patent merges the buffer function directly into the memory device by integrating SRAM cells on the same die. This combination of buffer and memory array in a single integrated structure eliminates external buffering requirements and reduces data transfer latency, significantly improving I/O speed while preserving the high memory density provided by the 3D architecture.
3Productivity
If more space is allocated for peripheral circuits, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
By moving peripheral circuits to vertical layers rather than expanding them horizontally, the patent achieves high device performance without increasing the overall die footprint. This vertical arrangement reduces the total manufacturing area required, leading to lower fabrication costs and improved ease of manufacture while maintaining excellent performance characteristics.
Solution Approach 2:
The nested integration of peripheral circuits within the vertical memory structure allows efficient use of available space. The circuits are positioned to share fabrication processes and packaging with the memory array, reducing overall manufacturing complexity and cost while delivering high device performance through optimized signal paths and reduced parasitic effects.
Data Source
AI summary
Embodiments of a three-dimensional (3D) memory device and a method of operating the 3D memory device are provided. The 3D memory device includes an array of 3D NAND memory cells, an array of static random-access memory (SRAM) cells, and a peripheral circuit. The array of SRAM cells and the peripheral circuit arranged at one side are bonded with the array of 3D NAND memory cells at another side to form a chip. Data is received from a host through the peripheral circuit, buffered in the array of SRAM cells, and transmitted from the array of SRAM cells to the array of 3D NAND memory cells. The data is programmed into the array of 3D NAND memory cells.