3D Memory SSG Isolation Structure for Leakage Prevention
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Solution Overview
Problem
In 3D memory devices, the formation of semiconductor plugs in channel holes is often unsatisfactory, leading to short-circuits between the source select gate (SSG) and the substrate due to etch loading effects and defects, resulting in leakage current and device failure, and alignment issues due to trench formation in the substrate.
Innovation Solution
The introduction of an isolation structure that extends vertically into the substrate to separate the SSG sacrificial layer from the channel structures, preventing short-circuits and defects, and the simultaneous formation of the isolation structure, alignment mark, and SSG cut in the same process to avoid additional fabrication steps and costs, ensuring a flat surface for alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolation structure is introduced to separate the SSG and channel structures, then short-circuits and leakage current are prevented, but device complexity and fabrication process complexity increase
Solution Approach 1:
The device is divided into separate regions by the isolation structure, which segments the substrate into distinct areas for the SSG and channel structures. This segmentation prevents electrical interaction between adjacent components, eliminating short-circuit paths and leakage current while maintaining clear functional boundaries.
Solution Approach 2:
The isolation structure serves as an intermediary element positioned between the SSG and channel structures. This intermediate component acts as an electrical barrier that prevents direct contact and harmful electrical interactions, while allowing both structures to function independently without modification to their original designs.
2Productivity
If the isolation structure, alignment mark, and SSG cut are formed simultaneously, then additional fabrication steps and costs are avoided, but manufacturing precision requirements increase
Solution Approach 1:
The formation of the isolation structure, alignment mark, and SSG cut is merged into a single fabrication step. By combining these three previously separate processes into one simultaneous operation, the total number of fabrication steps is reduced, improving productivity and reducing cumulative alignment errors that would occur with sequential processing.
Solution Approach 2:
The single fabrication step introduced serves multiple functions simultaneously: it creates the isolation structure for electrical separation, forms the alignment mark for subsequent processing steps, and defines the SSG cut geometry. This multi-functional approach eliminates the need for separate dedicated steps for each feature.
3Quantity of substance
If planar memory cells are scaled to smaller sizes, then memory density increases, but process technology becomes challenging and costly
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell scaling to three-dimensional vertical stacking architecture. By moving into the vertical dimension, the design achieves higher memory density without requiring further reduction of lateral feature sizes, thereby avoiding the escalating fabrication difficulties and costs associated with extreme miniaturization.
Data Source
AI summary
Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a semiconductor layer, a memory stack over the semiconductor layer, first channel structures each extending vertically through the memory stack in an edge region, and an isolation structure. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. At least one of conductive layers toward the semiconductor layer is a source select gate line (SSG). The isolation structure extends vertically through the SSG and into the semiconductor layer. The memory stack includes a core array region, a staircase region, and the edge region being laterally between the core array region and the staircase region. At least one of the first channel structures extends through the isolation structure and is separated from the SSG through the isolation structure.