3D Memory Stack Bonding Structure for Short-Circuit Reliability

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Solution Overview

Problem

There is an increasing demand for high-capacity data storage in semiconductor devices, and existing technologies face challenges in enhancing the reliability of three-dimensionally arranged memory cells.

Innovation Solution

A semiconductor device is designed with a first substrate structure and a second substrate structure, featuring gate electrodes, channel structures, separation regions, and insulating regions that are stacked and connected through bonding metal layers, with the insulating regions having inclined side surfaces to improve reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If three-dimensionally arranged memory cells are used to increase data storage capacity, then storage capacity is improved, but reliability deteriorates due to increased complexity and potential defects

Engineering Contradiction:
Improvedata storage capacityVSAvoiddevice reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The device is divided into multiple substrate structures (first substrate structure and second substrate structure) that are stacked and bonded together. This segmentation allows the complex three-dimensional memory structure to be divided into manageable modules, improving reliability through modular design while maintaining high storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Bonding metal layers are introduced as intermediary elements to connect the first and second substrate structures. These bonding metal layers serve as mediators that ensure reliable electrical and mechanical connections between stacked substrates, thereby improving overall device reliability while enabling increased storage capacity through vertical stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If multiple substrate structures are stacked to increase storage capacity, then data storage capacity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidstructure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The complex three-dimensional memory structure is divided into multiple separate substrate structures that can be manufactured independently and then bonded together. This segmentation simplifies the manufacturing process for each individual substrate while achieving high storage capacity through the stacked configuration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple substrate structures are stacked in a nested configuration, with the second substrate structure positioned on top of the first substrate structure. This nesting approach allows complex functionality to be achieved through simple vertical stacking, reducing manufacturing complexity compared to creating the entire structure in a single complex fabrication process.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If bonding metal layers are used to connect substrate structures, then reliability is improved through better connections, but manufacturing complexity increases

Engineering Contradiction:
Improveconnection reliabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Bonding metal layers are introduced as intermediary elements to connect the first and second substrate structures. These bonding metal layers serve as mediators that ensure reliable electrical and mechanical connections between stacked substrates, thereby improving overall device reliability while enabling increased storage capacity through vertical stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12362302B2Semiconductor devices and data storage systems including the same
Publication Date: 2025.07.15 SAMSUNG ELECTRONICS CO LTD
  • US12362302B2 patent drawing
  • US12362302B2 patent drawing
  • US12362302B2 patent drawing

AI summary

A semiconductor device includes a first substrate structure including a substrate, circuit elements, and first bonding metal layers, and a second substrate structure connected to the first substrate structure. The second substrate structure includes a plate layer, gate electrodes stacked in a first direction below the plate layer, separation regions penetrating through the gate electrodes and extending in a second direction and spaced apart from each other in the second direction, an insulating region extending from an upper surface of the plate layer and penetrating through the plate layer and at least one of the gate electrodes between the separation regions, and second bonding metal layers connected to the first bonding metal layers. The insulating region has inclined side surfaces such that a width of the insulating region decreases in a direction toward the first substrate structure.