3D Memory Stack Channel Structure for Reliable Cell Integration
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices is compromised as the number of memory cells stacked over the substrate increases, leading to integration challenges.
Innovation Solution
A semiconductor memory device structure is designed with a doped semiconductor layer extending into a hole, a core insulating pattern, and a channel pattern, along with a spacer pattern to maintain spacing and enhance electrical connectivity, thereby improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory cells stacked over the substrate is increased to improve integration, then the degree of integration is improved, but the operational reliability is deteriorated
Solution Approach 1:
The device is divided into multiple stacked memory cell layers, with each layer containing memory cells, interlayer insulating layers, and conductive patterns. This segmentation allows high integration while maintaining reliability through modular structure management
Solution Approach 2:
Interlayer insulating layers are introduced as intermediary structures between stacked memory cells to provide electrical isolation and mechanical support, enabling high-density stacking while maintaining operational reliability through proper insulation and stress management
2Area of stationary object
If the number of memory cells stacked over the substrate is increased to improve integration, then the area of substrate occupied is decreased, but the operational reliability is deteriorated
Solution Approach 1:
Memory cells are arranged in three-dimensional stacked configuration vertically over the substrate, transitioning from two-dimensional to three-dimensional layout. This reduces substrate area occupation while incorporating interlayer insulating layers and conductive patterns to maintain reliability in the vertical dimension
3Reliability
If the doped semiconductor layer extends into the hole to enhance electrical connectivity, then the turn-on current is increased, but the manufacturing precision is challenged
Solution Approach 1:
The doped semiconductor layer is formed to extend into the hole structure during the manufacturing process, establishing proper electrical connectivity and turn-on current characteristics before final device operation, ensuring reliable electrical performance
Solution Approach 2:
The doped semiconductor layer exhibits different properties in different regions: it extends into the hole where electrical connectivity is needed, while maintaining appropriate spacing in other regions. This local variation in structure and doping enables optimized electrical characteristics without compromising overall manufacturing precision
Data Source
AI summary
A semiconductor memory device includes: a stack structure including a first interlayer insulating layer, and a plurality of second interlayer insulating layers and a plurality of conductive patterns, which are alternately disposed under the first interlayer insulating layer; a hole penetrating the stack structure; a core insulating pattern, a memory pattern, and a channel pattern, disposed inside the hole; and a doped semiconductor layer disposed over the first interlayer insulating layer, the doped semiconductor layer extending to the inside of the hole.