3D Memory Stack Layout for High-Density CMOS Embedded Memory

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Solution Overview

Problem

Current semiconductor devices face challenges in integrating high-density embedded memory arrays with logic circuits, particularly in efficiently forming memory cells that can store and read/write single bits, while maintaining compatibility with nano-scale logic circuits and CMOS fabrication processes.

Innovation Solution

The semiconductor device incorporates a front-end-of-line (FEOL) and back-end-of-line (BEOL) portions, with memory cells including RRAM, PCRAM, or MRAM cells formed in the BEOL portion, utilizing a transistor array and conductive lines, dielectric layers, and memory stacks to create 1T1R type memory cells, allowing for reduced footprint and efficient operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If memory cells are formed in the BEOL portion using transistor array and memory stacks, then high-density embedded memory arrays with reduced footprint are achieved, but device complexity increases due to integration of multiple layers and components

Engineering Contradiction:

ImprovefootprintVSAvoidintegration complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar memory cell layouts to vertical stacking architecture, where memory stacks are formed in the third dimension above the transistor array in the BEOL portion. This vertical integration enables high-density memory arrays with reduced footprint by utilizing vertical space rather than horizontal expansion.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested structures where memory stacks are positioned above and connected to transistor arrays, with conductive lines and dielectric layers nested within and between these structures. This nesting approach maximizes space utilization and achieves high integration density.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Adaptability or versatility

If emerging memory technologies (RRAM, PCRAM, MRAM) are integrated into CMOS fabrication processes, then compatibility with nano-scale logic circuits is improved, but manufacturing precision requirements increase

Engineering Contradiction:

ImproveCMOS compatibilityVSAvoidfabrication precision

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent designs memory cell structures and fabrication processes that are universal across different emerging memory technologies (RRAM, PCRAM, MRAM) and compatible with standard CMOS fabrication processes. The same basic structure can accommodate different memory materials and mechanisms, enabling multi-functionality and broad adaptability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs parameter changes in material composition, layer thickness, and deposition conditions to accommodate different emerging memory technologies within the same CMOS fabrication framework. By adjusting these parameters, the same fabrication process can produce different types of memory cells with appropriate precision requirements.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11903221B2Three dimensional semiconductor device with memory stack

Publication Date: 2024.02.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.