3D Memory Stack Structure With Vertical Bit-Through Connections
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Solution Overview
Problem
The increasing demand for high integration in semiconductor devices leads to complex signal transmission paths between logic wafers and stacked memory wafers, requiring more active/passive elements and complicating the stack structure.
Innovation Solution
A semiconductor device with a circuit structure including a page buffer or decoder, featuring a stack structure with alternately stacked insulating layers and horizontal electrodes, and source lines and channel structures connected through these stacks, allowing for efficient electrical connections and reduced complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory wafers are sequentially stacked on a logic wafer to increase integration, then memory capacity increases, but signal transmission paths become increasingly complicated and more active/passive elements are required
Solution Approach 1:
The patent transitions from planar 2D wiring to 3D vertical stacking, where bit lines extend vertically through multiple memory wafer layers. This dimensional change allows signal transmission paths to be organized in the vertical dimension rather than spreading horizontally, reducing the complexity of interconnections between logic and multiple memory wafers while maintaining high memory capacity
Solution Approach 2:
The patent implements a nested structure where multiple memory wafer stacks are integrated around a central logic wafer. The bit lines pass through multiple stacked memory wafers in a nested configuration, with each memory wafer containing memory cells that are nested around the vertical bit line structure, thereby reducing the number of external interconnections needed
Data Source
AI summary
A semiconductor device including a circuit structure which includes a page buffer. A first stack structure bonded over the circuit structure. A first source line disposed on the first stack structure. A first channel structure connected to the first source line by passing through the first stack structure is provided. A second stack structure bonded over the first stack structure and the first source line. A second source line disposed on the second stack structure. A second channel structure connected to the second source line by passing through the second stack structure is provided. A first bit through electrode connected to the second channel structure by passing through the first stack structure is provided. The first channel structure and the second channel structure connected to the page buffer.