3D Semiconductor Memory Stack with Etch Stop Capacitor Contact
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Solution Overview
Problem
The integration limits of two-dimensional nonvolatile memory elements have been reached, necessitating the development of three-dimensional nonvolatile memory elements with improved reliability and manufacturing efficiency.
Innovation Solution
A semiconductor memory device is manufactured with a source stack, capacitor electrode, and contact plug structure, including alternately stacked insulating and conductive layers, and a cell etch stop pattern to enhance manufacturing ease and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional nonvolatile memory elements are used to improve manufacturing simplicity, then manufacturing ease is improved, but integration degree reaches a limit and reliability deteriorates
Solution Approach 1:
The patent transitions from two-dimensional memory element arrangement to three-dimensional stacked structure, where memory cells are arranged vertically across multiple layers. This dimensional change enables continued scaling and improved integration density while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes.
2Quantity of substance
If three-dimensional nonvolatile memory elements with complex stacked structures are used to improve integration degree, then integration degree is improved, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into repeating unit cells, each comprising channel layers, insulating layers, and electrode layers stacked in a standardized sequence. This modular segmentation allows complex 3D structures to be fabricated through iterative application of simple, standardized deposition and etching processes.
Solution Approach 2:
The stacked structure incorporates multi-functional layers that serve multiple purposes: channel layers provide both memory function and structural support, insulating layers provide both electrical isolation and mechanical spacing, and electrode layers serve both as capacitive elements and as interconnect structures. This multi-functionality reduces the number of separate components needed.
3Productivity
If capacitor electrodes are formed using cell etch stop pattern process to improve manufacturing efficiency, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
Cell etch stop patterns are formed in advance during the stack fabrication process, before capacitor electrode formation. These pre-formed patterns serve as ready-made masks and alignment references for subsequent capacitor electrode deposition, eliminating the need for separate alignment procedures and reducing overall manufacturing steps.
Data Source
AI summary
The present technology includes a semiconductor memory device. The semiconductor memory device includes a source stack, a capacitor electrode including a metal layer buried in the source stack, a stack including first insulating layers and second insulating layers alternately stacked on the source stack, and a contact plug passing through the stack and extending to be connected to the metal layer.