3D Memory Stack Isolation Structure for Select Transistor Reliability
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor devices deteriorates as the stacked number of memory cells increases, leading to reduced integration and performance.
Innovation Solution
A semiconductor device structure featuring a stack structure with alternately stacked conductive patterns and insulating layers, including a channel structure, tunnel insulating layer, cell storage pattern, and dummy storage pattern, along with a select conductive pattern in contact with the tunnel insulating layer, and an isolation structure between cell plugs, which improves the reliability by optimizing the arrangement and isolation of components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the stacked number of memory cells is increased to improve integration, then the area occupied by memory cells per unit area is reduced, but the operational reliability deteriorates
Solution Approach 1:
The patent introduces an isolation structure that segments the stack into multiple regions, dividing the continuous conductive patterns into isolated sections. This segmentation prevents error propagation between memory cells while maintaining high stacking density, thus improving reliability without sacrificing integration.
Solution Approach 2:
The isolation structure acts as an intermediary element between adjacent memory cells in the stack. It includes conductive patterns and insulating layers that mediate the electrical isolation, allowing each memory cell to operate independently and preventing operational failures from affecting the entire stack.
2Reliability
If storage patterns are placed between select conductive patterns and tunnel insulating layer for proper isolation, then reliability improves, but device complexity and manufacturing complexity increase
Solution Approach 1:
The patent merges the isolation function with the existing conductive patterns and insulating layers in the stack structure. Instead of adding separate storage patterns, the isolation structure utilizes the alternately stacked conductive patterns and insulating layers to achieve both electrical isolation and structural integrity, thereby reducing device complexity.
Solution Approach 2:
The conductive patterns and insulating layers in the isolation structure serve multiple functions: they provide electrical isolation between memory cells, maintain structural support for the stacked configuration, and enable proper positioning of channel structures. This multi-functionality eliminates the need for additional dedicated storage patterns.
3Reliability
If storage patterns are placed between select conductive patterns and tunnel insulating layer for testing, then reliability verification improves, but manufacturing complexity and process time increase
Solution Approach 1:
The isolation structure with conductive patterns and insulating layers provides self-testing capabilities through its inherent electrical isolation properties. The structure enables verification of isolation effectiveness during normal operation without requiring separate test structures or additional manufacturing steps, thus improving testability while maintaining ease of manufacture.
Data Source
AI summary
A semiconductor device includes: a stack structure including conductive patterns and stack insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; a tunnel insulating layer surrounding the channel structure; a cell storage pattern surrounding the tunnel insulating layer; and a dummy storage pattern surrounding the tunnel insulating layer, the dummy storage pattern being spaced apart from the cell storage pattern. The conductive patterns include a select conductive pattern in contact with the tunnel insulating layer.