3D Memory Die Stack Layout With Embedded Control Logic
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and reducing the size of memory devices while maintaining performance and simplifying designs, as control logic devices often consume more real estate and impede size reduction and performance improvements.
Innovation Solution
The formation of microelectronic devices with vertically stacked memory cells and control logic devices, where some control logic devices are placed within a second microelectronic device structure vertically between the first and third microelectronic device structures, allowing for a reduced horizontal footprint and increased memory density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If control logic devices are placed in a base control logic structure underlying the memory array, then control operations can be performed, but the horizontal footprint and device size increase
Solution Approach 1:
The patent transitions control logic devices from a two-dimensional planar arrangement in the base control logic structure to a three-dimensional vertical stacking configuration. Multiple control logic devices are positioned at different vertical levels (first control logic device in the first deck, second control logic device in the second deck), enabling control operations while significantly reducing the horizontal footprint of the memory device.
2Adaptability or versatility
If control logic devices are arranged in a conventional planar configuration, then device functionality is maintained, but memory density is reduced
Solution Approach 1:
The invention vertically stacks control logic devices across multiple decks rather than arranging them in a conventional planar configuration. This three-dimensional arrangement maintains all necessary control logic functionality while increasing the quantity of memory cells that can be packed into the same horizontal area, thereby improving memory density.
Solution Approach 2:
The patent nests control logic devices within the vertical structure of the memory device, with control logic devices positioned between memory cell decks. This nested arrangement allows control functionality to be integrated within the memory structure itself, maximizing the use of available space and increasing overall memory density.
3Manufacturing precision
If processing conditions are optimized for memory array formation, then memory cell quality is improved, but control logic device configurations are limited
Solution Approach 1:
The patent segments the fabrication process into distinct stages: first forming the memory array with optimized processing conditions for high-quality memory cells, then subsequently adding control logic devices in separate decks. This segmentation allows each component to be optimized independently - memory cells achieve high quality through optimized processing conditions, while control logic devices gain configuration flexibility through later integration at different vertical levels.
Data Source
AI summary
A microelectronic device comprises a first microelectronic device structure, a second microelectronic device structure vertically neighboring the first microelectronic device structure, and a third microelectronic device structure vertically neighboring the second microelectronic device structure. The first microelectronic device structure comprises a first memory array region and the third microelectronic device structure comprises a second memory array region. The second microelectronic device structure comprises a control logic region comprising a first sub word liner driver region comprising transistor structures in electrical communication with structures of the first microelectronic device structure and a second sub word line driver region comprising additional transistor structures in electrical communication with structures of the third microelectronic device structure. Related microelectronic devices, electronic systems, and methods are also described.