3D Cylindrical Memory Stack for Low-Leakage High-Density Cells
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Solution Overview
Problem
Current planar memory cells face challenges in scaling down due to increased current leakage, power consumption, and decreased retention times, while capacitor-less one transistor memory structures require further optimization for manufacturable integration and operation.
Innovation Solution
A method for forming a three-dimensional memory structure with a cylindrical body surrounded by multiple gates, including a word line and plate line gates, which eliminates the need for capacitors and improves data retention and operation speeds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then device density is improved, but current leakage increases and retention time decreases
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) vertical architecture. The memory stack extends vertically with alternating conductive and dielectric layers, allowing density improvement without the severe scaling penalties that plague planar structures. This dimensional change enables continued scaling while maintaining better charge retention characteristics.
Solution Approach 2:
The patent implements a nested structure where a cylindrical body is surrounded by multiple concentric gates (first gate, second gate, third gate) at different vertical levels. Each gate is embedded within dielectric layers, creating a nested configuration that provides enhanced control over the channel region without increasing lateral footprint, thus improving density while maintaining reliability.
2Quantity of substance
If planar memory cells are scaled to smaller sizes, then device density is improved, but power consumption increases
Solution Approach 1:
By moving to 3D vertical architecture, the patent achieves higher density without the excessive current leakage that plagues scaled planar devices. The vertical stack configuration with multiple gates provides better electrostatic control, reducing leakage currents and thus power consumption while maintaining high density.
Solution Approach 2:
The patent applies different doping types and concentrations to different regions: the substrate and bottom conductive layer use first type dopants, while the cylindrical body uses second type dopants. The cap layer is also doped with first type dopants. This localized doping strategy optimizes carrier control and reduces leakage in specific regions, lowering overall power consumption.
3Quantity of substance
If capacitor-less one transistor memory structures are used, then device density is improved, but manufacturable integration and operation require further optimization
Solution Approach 1:
The patent segments the gate structure into multiple distinct gates (first gate, second gate, third gate) positioned at different vertical levels within the memory stack. Each gate can be independently controlled through separate word lines, providing finer-grained control over the memory cell operation. This segmentation enables better manufacturability by allowing independent optimization of each gate's characteristics.
Solution Approach 2:
The memory stack structure serves multiple functions: it provides the channel region, contains the gates for control, includes dielectric layers for isolation and insulation, and incorporates conductive layers for interconnection. This multi-functional integration simplifies the manufacturing process by combining several components into a single vertically-stacked structure that can be formed through a unified fabrication sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed 3D memory structure enhances transistor carrier density, reduces leakage current, and increases program/erase speeds, providing faster operation and higher density compared to traditional DRAM.
Implementation Method 1
performing an oxidation process to treat exposed surface of the plurality of conductive layers of the memory stack and the bottom conductive layer to form an oxide layer
Implementation Method 2
doping the bottom conductive layer and the cap layer with a first type of dopant; doping the semiconductor structure with a second type of dopant opposite to the first type of dopant
Implementation Method 3
forming the semiconductor structure on the cap layer to fill the opening; forming the semiconductor material in the opening by a patterned epitaxial growth process
Data Source
AI summary
Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a memory stack on the bottom conductive layer, the memory stack comprising a plurality of alternatively arranged dielectric layers and conductive layers; forming an opening penetrating the memory stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and forming a plurality of interconnection structures to electrically connect the bottom conductive layer, the plurality of conductive layers of the memory stack, and the top contact.