3D Memory Cell Stack Layout With Upper-Level Multiplexer Integration
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the size and complexity of memory devices, as processing conditions and control logic structures hinder reductions in device size and performance improvements.
Innovation Solution
The formation of vertical stacks of memory cells with multiplexers and transistors in the uppermost levels of access devices, allowing for greater density and efficient electrical communication through conductive structures, and integration with control logic circuitry to form a microelectronic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If control logic devices are integrated within the base control logic structure underlying the memory array, then the memory device can operate with coordinated control, but the control logic devices consume excessive real estate and limit reductions in device size
Solution Approach 1:
The control logic functionality is segmented into two separate components: (1) control logic circuitry formed in a first semiconductor substrate, and (2) memory array formed in a second semiconductor substrate. This segmentation allows each component to be independently optimized and reduces the real estate consumption within the memory device while maintaining coordinated control through inter-substrate interconnects.
Solution Approach 2:
An interconnect structure acts as an intermediary between the control logic circuitry in the first substrate and the memory array in the second substrate. This intermediary enables electrical communication and coordinated operation while physically separating the components to reduce real estate consumption and allow independent optimization of each subsystem.
2Productivity
If the quantity and complexity of control logic devices are increased to handle higher memory array density, then more sophisticated control operations can be performed, but the control logic devices consume more real estate and impede performance improvements
Solution Approach 1:
By segmenting the control logic circuitry into a separate first substrate, the patent enables high-density memory arrays in the second substrate without being constrained by the real estate requirements of complex control logic devices. The control logic can be optimized independently for high-density operation while maintaining lower real estate consumption within the memory array structure.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture where control logic circuitry and memory array are formed in different substrates stacked vertically. This dimensional change allows high-density memory arrays to achieve greater productivity without increasing the lateral real estate footprint, as the control logic resides in a separate vertical layer.
3Reliability
If processing conditions are optimized for memory array formation over the base control logic structure, then memory cell performance is improved, but the control logic devices within the base control logic structure are limited in configuration and performance
Solution Approach 1:
The patent segments the fabrication process into two independent stages: (1) forming control logic circuitry in a first substrate under its own optimized processing conditions, and (2) forming the memory array in a second substrate under memory-optimized processing conditions. This segmentation allows each component to achieve its full performance potential without compromise while enabling independent optimization of control logic configuration and memory cell performance.
Solution Approach 2:
The control logic circuitry is formed in the first substrate as a preliminary action before the memory array is formed in the second substrate. This preliminary formation allows the control logic to be fully configured and optimized under its ideal processing conditions, and then integrated with the memory array without compromising either component's performance or adaptability.
Data Source
AI summary
A microelectronic device comprises a vertical stack of memory cells. The vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, a conductive pillar structure in electrical communication with the vertical stack of access devices, and an isolated conductive structure in electrical communication with a multiplexer comprising a vertically uppermost access device of the vertical stack of access devices. The microelectronic device further comprises a stack structure comprising conductive structures interleaved with insulative structures, at least some of the conductive structures individually in electrical communication with a memory cell of the vertical stack of memory cells and comprising a gate of an access device of the vertical stack of access devices. Related electronic systems and methods are also described.