3D Memory Stack Structure for Dense and Reliable NAND Storage
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Solution Overview
Problem
There is a need for semiconductor devices that can increase integration density and reliability, particularly in data storage systems, as existing two-dimensional semiconductor devices face limitations in storage capacity.
Innovation Solution
The semiconductor device includes a stack structure with alternating interlayer insulating layers and gate layers, a memory vertical structure, a support vertical structure with an air gap, and gate contact plugs, which are designed to enhance integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional cell arrangement is used, then manufacturing process is simple, but storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional cell arrangement to three-dimensional stack structure with multiple levels (first level, second level, third level), thereby increasing storage capacity by utilizing vertical space dimension. The stack structure includes alternating insulating layers and charge trapping layers arranged vertically, enabling higher integration density without complicating the fundamental manufacturing process flow.
2Manufacturing precision
If three-dimensional stack structure is used, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The stack structure is segmented into discrete alternating layers of insulating material and charge trapping material, with each layer formed through separate deposition steps. This segmentation allows for precise control of individual layer thickness and composition, facilitating accurate alignment and reducing manufacturing precision requirements despite the three-dimensional complexity.
Solution Approach 2:
The patent employs parameter changes in the form of alternating material compositions and thicknesses within the stack structure. By varying the dielectric constants, trap densities, and layer thicknesses of alternating insulating and charge trapping layers, the design optimizes electrical performance while maintaining manufacturability through standard deposition parameters.
3Reliability
If gate layers are spaced apart in vertical direction, then electrical isolation is improved, but device area increases
Solution Approach 1:
The patent resolves the area-isolation contradiction by moving the isolation function from the horizontal plane to the vertical dimension. Gate layers are stacked vertically with spacing between them, providing electrical isolation through the vertical arrangement rather than requiring large horizontal separation. This three-dimensional gating structure achieves effective isolation while maintaining compact device footprint.
Solution Approach 2:
Multiple gate layers are nested vertically within the stack structure, with each gate layer positioned at different heights and electrically isolated from others through the intervening insulating layers. This nested arrangement of gated regions in the vertical dimension provides comprehensive electrical isolation for multiple memory strings while occupying minimal planar area.
Data Source
AI summary
A semiconductor device includes a structure including a stack structure including a first stack structure and a second stack structure on the first stack structure; a memory vertical structure penetrating the structure; a support vertical structure including a portion penetrating the structure and including an air gap; and a peripheral contact plug, wherein the first and second stack structures includes interlayer insulating layers and gate layers alternately stacked, a side of the memory vertical structure includes a slope changing portion, the peripheral contact plug includes an upper region disposed on a level higher than an upper surface of an uppermost gate layer, the upper region of the peripheral contact plug includes a first region, a second region and a connection region between the first and second regions, and the connection region has a slope different from a slope of at least one of the first and second regions.