3D Memory Stack Structure With Source Contacts for Noise Isolation
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity and electrical performance while maintaining integration density.
Innovation Solution
The semiconductor device incorporates a stack structure with vertically stacked gate electrodes and conductive layers, separated by insulating layers, along with vertical memory structures and source contact plugs, which enhance electrical connectivity and prevent noise generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged three-dimensionally instead of two-dimensionally, then data storage capacity is increased, but device complexity increases
Solution Approach 1:
The patent implements a three-dimensional stack structure with gate electrodes, insulating layers, and conductor stacks arranged vertically across multiple levels. This vertical stacking approach transitions from traditional two-dimensional memory cell arrangement to three-dimensional configuration, enabling increased data storage capacity by utilizing the vertical dimension for additional storage layers while maintaining a compact footprint on the semiconductor substrate.
Solution Approach 2:
The memory device is segmented into multiple functional stacks including first stack regions with gate electrodes, second stack regions with conductor stacks, insulating layers, and separation structures. Each stack operates as an independent functional unit that can be individually controlled through source contact plugs and bitlines, allowing parallel operation and reducing overall device complexity through modular organization.
2Quantity of substance
If stack structure with vertically stacked gate electrodes and conductive layers is implemented, then integration density is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent achieves increased integration density by stacking gate electrodes, insulating layers, and conductor stacks vertically in multiple levels. This three-dimensional arrangement packs more memory elements into a smaller planar area by utilizing the vertical dimension, thereby increasing the number of storage cells per unit area without requiring proportionally smaller feature sizes.
Solution Approach 2:
The patent employs preliminary formation of plate patterns with gaps, followed by sequential deposition of insulating layers and conductor stacks in predetermined locations. Source contact plugs are pre-positioned to contact specific conductive layers, and separation structures are formed in advance to define stack regions. This preliminary action approach ensures precise alignment and reduces manufacturing complexity by establishing a structured framework before final assembly.
3Reliability
If source contact plugs are used to electrically connect conductive layers and plate pattern, then electrical performance is improved, but noise interference increases
Solution Approach 1:
The patent introduces separation structures as intermediary elements positioned between adjacent stack regions. These separation structures act as electrical isolators that prevent noise coupling and interference between neighboring memory stacks while still allowing source contact plugs to establish necessary electrical connections to the plate pattern and conductive layers within each stack region.
Solution Approach 2:
The patent extracts and removes potential noise sources by creating gaps in the plate pattern and positioning separation structures to isolate conductive layers from adjacent stacks. Source contact plugs are selectively connected to specific conductive layers while leaving others isolated, thereby extracting only the necessary electrical connections and removing unnecessary coupling paths that could transmit noise interference.
Data Source
AI summary
A semiconductor device may include: a semiconductor substrate; a peripheral circuit structure on the semiconductor substrate; a plate pattern on the peripheral circuit structure and having a gap; and a stack structure on the plate pattern and including a first stack region and a second stack region. The first stack region may include gate electrodes stacked in a vertical direction perpendicular to an upper surface of the semiconductor substrate, and the second stack region may include both a conductor stack region including conductive layers stacked in the vertical direction and an insulator stack region including molded insulating layers at substantially the same height level as the conductive layers. The semiconductor device may also include vertical memory structure that extends through the first stack region; and source contact plugs electrically connected to at least one of the conductive layers of the conductor stack region and contacting the plate pattern.