3D Semiconductor Memory Device Vertical Stack Integration
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in integration density due to the high cost and complexity of forming fine patterns, leading to a need for three-dimensional semiconductor memory devices that can enhance electrical characteristics and increase storage capacity.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a peripheral circuit structure and a cell array structure, featuring stack structures, separation structures, and contact plugs to improve integration density and electrical connectivity, allowing for increased storage capacity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional semiconductor memory devices are used, then manufacturing processes are simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory structures. Multiple memory cell layers are stacked in the vertical direction, with each layer containing memory cells formed over different regions of the substrate. This dimensional change enables significantly higher integration density without requiring proportionally more complex manufacturing processes, as the vertical stacking can be achieved through sequential formation of multiple layers using standard semiconductor fabrication techniques.
2Manufacturing precision
If fine patterns are formed to increase integration density, then storage capacity increases, but manufacturing cost increases
Solution Approach 1:
Instead of increasing integration density through finer lateral patterning which requires expensive advanced lithography equipment, the patent stacks multiple memory cell layers vertically. This approach achieves high integration density using conventional lithography processes, thereby avoiding the need for extremely high-priced apparatuses while still attaining the desired storage capacity.
Solution Approach 2:
The memory device is divided into multiple discrete memory cell layers stacked vertically, with each layer being a separate manufacturable unit. This segmentation allows each layer to be formed using standard manufacturing processes, and the layers are then stacked to achieve high integration density without requiring a single complex ultra-fine patterning step.
3Manufacturing precision
If three-dimensional stack structures are implemented, then integration density improves, but electrical connection complexity increases
Solution Approach 1:
The patent introduces separation structures positioned between adjacent memory cell layers to provide mechanical support and electrical isolation. These separation structures include insulating materials and conductive plugs that facilitate vertical electrical connections between layers while maintaining structural integrity. The intermediaries simplify the overall electrical connection architecture by providing dedicated pathways for signal and power lines to traverse through the stacked structure.
Solution Approach 2:
The patent extracts the electrical connection function into separate dedicated structures - specifically, conductive plugs embedded in the separation structures and independent interconnect layers. This separation of concerns allows the memory cell layers to focus on storage functionality while the extracted connection structures handle the complexity of vertical electrical interconnections, thereby managing the overall device complexity more effectively.
Data Source
AI summary
A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.