3D Semiconductor Memory Stack with Vertical Channel Reliability
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Solution Overview
Problem
Existing two-dimensional or planar semiconductor devices face limitations in integration due to the need for expensive processing equipment to achieve finer patterns, which restricts the degree of integration and reliability.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure comprising dielectric layers, electrodes, and stopper layers, along with a vertical channel structure that penetrates the stack, optimizing the arrangement of memory cells for improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used to increase integration, then manufacturing cost increases due to expensive processing equipment, but integration degree is limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with bit lines extending in the first direction and word lines in the second direction, enabling higher integration density without requiring finer pattern dimensions that would demand expensive processing equipment
2Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing cost is reduced, but integration degree is limited
Solution Approach 1:
The invention employs vertical stacking of multiple memory cell layers along the third direction (vertical axis), with each layer containing memory cells defined by bit lines in the first direction and word lines in the second direction. This three-dimensional arrangement dramatically increases the number of memory cells per unit area without requiring reduction in feature size, thereby achieving high integration degree while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The memory device is divided into multiple stacked memory cell layers, where each layer can be independently formed and processed. The bit lines and word lines are segmented across different layers, with connection holes providing vertical electrical connections between layers, allowing modular fabrication and higher overall integration
3Productivity
If three-dimensional stacked structure is implemented, then integration density increases, but process complexity increases
Solution Approach 1:
The three-dimensional memory structure is segmented into multiple discrete layers (first memory cell layer, second memory cell layer, etc.), with each layer containing complete sets of bit lines, word lines, and memory cells. Connection holes are selectively formed to establish vertical electrical paths between corresponding elements in different layers, allowing systematic and modular fabrication that manages complexity through structured repetition
Solution Approach 2:
The patent employs universal structural motifs that are repeated across layers: bit lines extending in the first direction, word lines in the second direction, and connection holes providing vertical connectivity. This modular, repeating architecture allows the same fabrication processes to be applied across multiple layers, reducing overall process complexity despite the increased integration density
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.