3D Charge-Storage Memory Stack for Lower Series Resistance
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Solution Overview
Problem
In three-dimensional memory cell arrays, increased series resistance due to stacked memory elements leads to current loss and heat generation, and the interface between semiconductor and insulator can form trap centers, affecting transistor performance.
Innovation Solution
A semiconductor device structure with a stack configuration including specific insulators, conductors, and oxides, where the oxide layers have varying energy gaps and compositions, such as In, Ga, and Zn, to reduce series resistance and inhibit trap center formation, along with a manufacturing method to form these layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but series resistance increases causing current loss and heat generation
Solution Approach 1:
The memory cell array is divided into multiple independently controllable banks (first memory bank, second memory bank, etc.), each with separate word lines and bit lines. This segmentation allows selective activation of specific banks, reducing the total resistance path when accessing memory cells and minimizing current loss in the stacked structure.
Solution Approach 2:
The patent transitions from planar memory architecture to three-dimensional stacked memory cells, arranging memory elements vertically across multiple layers. This dimensional change increases storage capacity per unit area while incorporating intermediate conductive layers and insulating structures to manage the increased series resistance inherent in vertical stacking.
2Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but heat generation increases in the memory cell array
Solution Approach 1:
The stacked memory structure is divided into multiple banks with independent control, allowing selective operation of subsets of memory cells. This reduces the total number of simultaneously active cells, thereby reducing overall heat generation while maintaining high storage capacity through selective access to different banks.
Solution Approach 2:
Different regions of the stacked memory structure have optimized local properties - specific insulating materials and conductive layers are positioned at particular locations to manage heat distribution, with intermediate layers providing thermal management capabilities in high-density stacked regions.
3Device complexity
If semiconductor is in direct contact with insulator to simplify structure, then device complexity is reduced, but trap centers form at the interface affecting transistor performance
Solution Approach 1:
An intermediate layer is introduced between the semiconductor and insulator interfaces where memory cells are formed. This intermediate layer acts as a mediator that prevents direct contact between the semiconductor and insulator materials, thereby eliminating trap center formation at the interface while maintaining the simplified stacked structure architecture.
Data Source
AI summary
A semiconductor device having a large storage capacity per unit area is provided. The semiconductor device includes a stack, and the stack includes a first insulator, a first conductor over the first insulator, and a second insulator over the first conductor. The stack includes a first opening provided in the first insulator, the first conductor, and the second insulator and an oxide on the inner side of the first opening. Furthermore, in the first opening, a third insulator is positioned on the outer side of the oxide, a second conductor is positioned on the inner side of the oxide, and a fourth insulator is positioned between the oxide and the second conductor. The third insulator includes a gate insulating layer positioned at a side surface of the first opening, a tunnel insulating layer positioned on the outer side of the oxide, and a charge accumulation layer positioned between the gate insulating layer and the tunnel insulating layer.