3D Memory Cell Stack Structure for Integration and Retention
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Solution Overview
Problem
The existing semiconductor devices face limitations in degree of integration and operational reliability due to the constraints in two-dimensional memory cell formation, necessitating the development of three-dimensional stacking of memory cells to enhance integration and stability.
Innovation Solution
A semiconductor device structure featuring stacked gate lines, insulating cores, channel patterns, and a capping layer, along with a manufacturing method that includes forming specific barrier patterns and channel patterns to optimize the arrangement and connection of memory cells, allowing for improved integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional memory cell formation is used, then manufacturing process is simpler, but degree of integration reaches limitation
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional stacking by forming multiple memory cells vertically along the thickness direction of the substrate. Memory cells are stacked in the third dimension (vertical direction) using alternating conductive layers and insulating layers, enabling higher integration density without increasing planar area.
Solution Approach 2:
The patent implements nested structure where conductive layers and insulating layers are alternately stacked, with each layer nested within the vertical stack. The memory cells are formed by nesting multiple functional layers (conductive layers, insulating layers, charge trapping layers) within a single vertical column, achieving three-dimensional integration.
2Productivity
If three-dimensional stacking of memory cells is implemented, then degree of integration is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the complete stack of conductive layers and insulating layers before etching the memory cell regions. This preliminary formation of the vertical stack structure ensures that all layers are properly aligned and positioned before the memory cell patterns are created, reducing the precision requirements during the etching process.
Solution Approach 2:
The patent divides the continuous stack into discrete memory cell regions through selective etching. The stack is segmented into individual memory cells by removing portions of the conductive and insulating layers in a controlled manner, creating isolated memory cell structures while maintaining the integrity of the overall three-dimensional arrangement.
3Reliability
If three-dimensional stacking is used, then operational reliability should improve, but structural stability becomes more challenging
Solution Approach 1:
The patent uses composite material structure with alternating conductive layers and insulating layers. The insulating layers provide mechanical support and electrical isolation, while the conductive layers provide electrical functionality. This composite structure enhances both the structural stability and operational reliability of the three-dimensional stacked memory device.
Solution Approach 2:
The insulating layers act as intermediary elements between the conductive layers in the vertical stack. These intermediary insulating layers provide mechanical support to maintain the structural integrity of the stack, while also providing electrical isolation to ensure proper operational reliability of adjacent memory cells.
Data Source
AI summary
A semiconductor device including: a gate structure including stacked gate lines; an insulating core located in the gate structure and including a first long axis and a first short axis; a memory layer surrounding the insulating core; first channel pattern and a second channel pattern located facing each other along the first long axis, wherein the first channel pattern and the second channel pattern are located between the insulating core and the memory layer; and a capping layer located between the first channel pattern and the second channel pattern.