3D Memory Stack Separation Structure for High-Density Fabrication
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Solution Overview
Problem
Existing two-dimensional semiconductor devices face limitations in integration due to the need for expensive processing equipment and practical limitations in increasing pattern fineness, hindering high integration and high performance while maintaining low manufacturing costs.
Innovation Solution
A three-dimensional semiconductor memory device with a stack structure and mold structure, featuring separation structures and vertical channel structures, which includes alternately stacked interlayer dielectric and sacrificial layers, enhancing reliability and simplifying fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional or planar semiconductor devices are highly integrated to meet high performance and low manufacturing cost requirements, then integration density increases, but the need for expensive processing equipment and practical limitations in increasing pattern fineness worsen
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically arranged memory cells. The stack structure with alternating dielectric layers and electrode layers extends in the vertical direction, enabling high integration density without requiring finer lateral patterning. This dimensional change allows achieving high productivity while avoiding the need for expensive ultra-fine patterning equipment.
2Manufacturing precision
If pattern fineness is increased to improve integration of two-dimensional semiconductor devices, then integration density increases, but expensive processing equipment is required
Solution Approach 1:
The invention forms memory cells in three dimensions with vertical stacking of electrode layers and dielectric layers. This approach achieves high manufacturing precision through vertical layering rather than lateral patterning, avoiding the need for expensive ultra-fine lithography equipment while maintaining high integration density.
Solution Approach 2:
The memory device is segmented into multiple thin electrode layers and dielectric layers stacked vertically. Each layer can be formed using standard thin-film deposition techniques, avoiding the need for single-step ultra-fine patterning. This segmentation into manageable layers reduces manufacturing complexity and equipment requirements.
3Productivity
If three-dimensional vertically arranged memory cells are formed to achieve high integration, then integration density increases, but fabrication process complexity increases
Solution Approach 1:
Multiple functional layers (electrode layers, dielectric layers, charge trapping layers) are merged into a single vertical stack structure. This integrated stack is formed using sequential deposition and patterning steps that can be automated, reducing overall fabrication process complexity despite the three-dimensional architecture.
Solution Approach 2:
The dielectric layers and electrode layers are pre-formed as a complete stack structure before final patterning and contact formation. This preliminary stacking simplifies subsequent processing steps by providing a ready-made three-dimensional framework that requires minimal additional complex operations.
Data Source
AI summary
Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.