3D Memory Stack With Split Peripheral Circuits for Higher Density

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in increasing memory storage density due to physical limitations, electrical interference, and manufacturing difficulties, particularly in three-dimensional (3D) semiconductor devices.

Innovation Solution

The semiconductor device is designed with semiconductor structures and control structures stacked together, where each semiconductor structure includes a memory array and a first circuitry, and the control structure includes second circuitries connected to the memory arrays. This configuration allows for separate manufacturing of the semiconductor structures and control structures, reducing thermal budget limitations and enabling more efficient use of space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory arrays are placed closer together to increase density, then storage density improves, but electrical interference between neighboring arrays increases

Engineering Contradiction:

Improvememory storage densityVSAvoidelectrical interference

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from planar arrangement of memory arrays to a three-dimensional stacked architecture. Multiple semiconductor structures (each containing memory arrays) are stacked vertically along a direction perpendicular to the substrate, enabling increased storage density without reducing lateral separation distances between arrays. This vertical stacking allows memory arrays to be positioned closer in terms of lateral footprint while maintaining adequate spacing to minimize electrical interference through the use of bonding layers and interconnection structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the memory device into multiple independent semiconductor structures, each containing its own memory arrays and control circuitry. These segmented structures are then stacked and interconnected through bonding layers. This segmentation allows each memory array to be isolated within its own semiconductor structure, reducing electrical interference between arrays while achieving high density through vertical stacking. The bonding layers act as isolation barriers that further minimize interference between stacked structures.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If control circuitry is integrated with memory arrays on the same substrate, then device complexity is reduced, but thermal budget limitations and manufacturing difficulties increase

Engineering Contradiction:

Improvedevice structure integrationVSAvoidmanufacturing process complexity

Core Design Contradiction:

Device complexityVSEase of manufacture

Solution Approach 1:

The patent separates control circuitry from memory arrays by placing them in different semiconductor structures. Each semiconductor structure contains either memory arrays or control circuitry, but not both. These separate structures are then stacked and interconnected through bonding layers and conductive interconnection structures. This segmentation allows each component to be optimized and manufactured independently, avoiding thermal budget limitations and manufacturing difficulties associated with integrating both on the same substrate.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces bonding layers and conductive interconnection structures as intermediaries between semiconductor structures containing memory arrays and those containing control circuitry. These intermediary elements enable electrical connection between separated components while allowing independent manufacturing and optimization of each semiconductor structure. The bonding layers serve as both mechanical bonding interfaces and electrical interconnection media.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Quantity of substance

If three-dimensional stacking is implemented to increase density, then storage capacity improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improvememory cell capacityVSAvoidstacking alignment precision

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent incorporates bonding layers on the surfaces of semiconductor structures before stacking. These pre-formed bonding layers provide alignment features and tolerance compensation mechanisms that facilitate precise stacking. The bonding layers are prepared in advance with appropriate thicknesses and material properties that enable alignment during the bonding process, reducing the stringency of alignment precision requirements while still achieving high-density stacking.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250293188A1Managing peripheral circuitries in semiconductor devices

Publication Date: 2025.09.18 YANGTZE MEMORY TECH CO LTD

AI summary

Systems, devices, and formation methods for a semiconductor device are provided. In one aspect, a semiconductor device includes semiconductor structures and at least one control structure. Each of the semiconductor structures includes a memory array and a first circuitry coupled to the memory array. The control structure includes second circuitries for the semiconductor structures. Each of the second circuitries is coupled to a memory array of a respective semiconductor structure of the semiconductor structures. The semiconductor structures and the at least one control structure are stacked together along a direction.