3D Semiconductor Memory Stack Structure
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Solution Overview
Problem
The integration density of two-dimensional semiconductor devices is limited by expensive processing equipment, making it difficult to increase integration without significant cost, whereas three-dimensional semiconductor memory devices offer a solution by arranging memory cells in a vertical stack structure, avoiding the need for expensive equipment.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stack structure that includes multiple layers vertically stacked on a substrate, featuring bit lines, gate lines, semiconductor patterns, and word lines, along with capacitor electrodes, allowing for increased integration without the need for expensive processing equipment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited by expensive processing equipment
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked vertically along the third direction perpendicular to the substrate, enabling increased integration density without requiring finer lateral patterning. This dimensional change allows achieving higher integration using relatively simple processing equipment.
2Manufacturing precision
If expensive processing equipment is used to increase pattern fineness, then integration density improves, but manufacturing cost increases significantly
Solution Approach 1:
Instead of improving lateral pattern fineness using expensive equipment, the patent achieves integration density improvement by stacking memory cells vertically in the third direction. This approach obtains the effect of increased integration without the need for costly advanced lithography equipment.
Solution Approach 2:
The memory device is segmented into multiple independently formable memory cell stacks arranged vertically. Each stack can be formed through sequential deposition and etching processes, allowing integration density to scale with the number of stacked layers rather than requiring proportionally finer lateral patterning at each level.
Data Source
AI summary
A semiconductor memory device includes a stack structure having a plurality of layers vertically stacked on a substrate, each layer including, a first bit line and a gate line extending in a first direction, a first semiconductor pattern extending in a second direction between the first bit line and the gate line, the second direction intersecting the first direction, and a second semiconductor pattern adjacent to the gate line across a first gate insulating layer, the second semiconductor pattern extending in the first direction, a first word line adjacent to the first semiconductor pattern and vertically extending in a third direction from the substrate, a second bit line connected to an end of the second semiconductor pattern and vertically extending in the third direction from the substrate, and a second word line connected to another end of the second semiconductor pattern and vertically extending in the third direction.