3D Memory Cell Stack With Stepped Word Lines for Low Capacitance
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Solution Overview
Problem
The challenge in semiconductor technology is to increase memory cell density while reducing parasitic capacitance, which is limited by the structural constraints of traditional memory cells.
Innovation Solution
A semiconductor device with a three-dimensional structure is fabricated by forming a stack body of alternating semiconductor layers and etch stopper layers, etching to create steps and slits, replacing etch stopper layers with sacrificial dielectric layers, and converting these into word lines, along with forming contact plugs to enhance memory cell integration and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory cell size is reduced to increase net die, then net die increases, but parasitic capacitance increases and structural limitations arise
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking. Multiple memory cells are stacked vertically along the thickness direction, enabling increased net die area utilization while maintaining reduced cell footprint. The word lines extend in the first direction, bit lines in the second direction, and stacking occurs in the third direction, creating a true 3D structure that resolves the contradiction between net die size and parasitic capacitance.
2Quantity of substance
If memory cell size is reduced, then integration density increases, but parasitic capacitance increases
Solution Approach 1:
By stacking memory cells vertically in the third direction, the patent achieves higher integration density without increasing lateral dimensions. This vertical arrangement reduces the lateral footprint of each cell while maintaining electrical isolation through the bit line structure, thereby increasing memory cell density without proportionally increasing parasitic capacitance.
Solution Approach 2:
The memory device is segmented into multiple independently stackable memory cells, each with its own bit line, word lines, and capacitor structure. This segmentation allows parallel operation of multiple cells, increasing effective density while distributing parasitic capacitance across separate cell units rather than concentrating it in a single large cell.
3Ease of manufacture
If conventional planar structure is used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent extends conventional planar manufacturing processes into the vertical dimension. The stack body is formed by alternating stacking of semiconductor layers and sacrificial layers in the thickness direction, then etching patterns are formed by removing portions of the stack body. This approach maintains compatibility with existing manufacturing techniques while achieving three-dimensional integration, thus preserving manufacturing simplicity while dramatically increasing integration density.
Data Source
AI summary
A method for fabricating a semiconductor device includes: forming a stack body by alternately stacking a plurality of semiconductor layers and a plurality of etch stopper layers over a substrate; forming a plurality of steps by etching a first portion of the stack body to stop at the etch stopper layer; forming a slit by etching a second portion of the stack body; replacing the etch stoppers of the steps with sacrificial dielectric layers through the slit; replacing the sacrificial dielectric layers with word lines; and forming contact plugs coupled to the word lines.