3D Vertical Stacked Semiconductor Memory Blocks for High Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a challenge in increasing the density of three-dimensional memory blocks within a predetermined area while maintaining the electrical characteristics of semiconductor memory devices.
Innovation Solution
The semiconductor memory device incorporates memory blocks stacked in multiple layers with vertically arranged bit and word lines, along with selection lines, to enhance memory cell density and prevent electrical deterioration, utilizing a structure that includes vertical channel layers, charge storage layers, and conductive layers to improve memory cell retention and reduce back tunneling phenomena.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced to increase the number of memory cells, then memory cell density increases, but electrical characteristics deteriorate
Solution Approach 1:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged in multiple layers above each other. This dimensional change allows increasing the number of memory cells without reducing individual cell size, thereby maintaining electrical characteristics while improving density.
Solution Approach 2:
The memory array is divided into multiple memory blocks stacked vertically, with each block containing memory cells arranged in distinct layers. This segmentation allows independent optimization of each layer's electrical characteristics while achieving high overall density through vertical integration.
2Quantity of substance
If three-dimensional memory blocks are stacked to increase density, then memory cell quantity increases, but electrical characteristics deteriorate
Solution Approach 1:
Each memory block layer is designed with locally optimized structures including vertical channels, charge storage layers, and control gates positioned at specific heights. This local quality optimization ensures that electrical characteristics are maintained in each layer while achieving high overall density through vertical stacking.
Solution Approach 2:
The patent introduces intermediate structures such as insulating layers, charge storage layers, and control gates between memory cell layers to mediate electrical interactions. These intermediary elements prevent electrical interference between stacked layers while maintaining signal integrity for read/write operations.
3Area of stationary object
If memory blocks are vertically stacked, then area efficiency improves, but interference between components increases
Solution Approach 1:
By moving from two-dimensional planar arrangement to three-dimensional vertical stacking, the patent achieves high area efficiency while separating components in the vertical dimension. This spatial separation in the third dimension reduces electromagnetic interference between bit lines, word lines, and control gates that would be problematic in planar configurations.
Solution Approach 2:
The patent extracts and separates critical control elements such as control gates and charge storage layers into distinct vertical positions within each memory block. This extraction allows independent control and reduces parasitic coupling between adjacent memory cell components, minimizing interference while maintaining compact vertical structure.
Data Source
AI summary
A semiconductor memory device includes a memory array including memory blocks stacked in a plurality of layers on a substrate, first vertical lines suitable for coupling bit lines, and second vertical lines suitable for coupling word lines of the memory blocks vertically stacked, wherein the memory blocks include selection lines vertically stacked and separated from each other, and the bit lines are coupled to the memory blocks and arranged in a plurality of layers.