3D Memory Structure With Stacked Peripheral Circuits for Higher Density
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Solution Overview
Problem
Planar memory cell technologies face challenges in scaling down due to limitations in feature size and fabrication costs, leading to upper density limits, which can be addressed by transitioning to three-dimensional (3D) memory architectures.
Innovation Solution
A method for forming a 3D memory device involves bonding two semiconductor structures, with a first semiconductor structure including a first transistor and a second semiconductor structure with memory cells, where the second transistor has a thinner gate dielectric layer and is fully depleted, and both structures are electrically connected through interconnects and isolation structures, enabling efficient memory cell formation and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but feature sizes approach a lower limit making planar processes challenging and costly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) memory architecture. The 3D memory structure includes vertically stacked memory cells with multiple tiers, allowing memory density to increase by utilizing the vertical dimension rather than continuing to scale lateral feature sizes. This resolves the contradiction by achieving higher density without requiring further reduction of already-minimal planar feature dimensions.
2Quantity of substance
If planar processes are continued to achieve higher density, then memory density is improved, but fabrication costs increase
Solution Approach 1:
By moving to 3D architecture with vertically stacked memory cells, the patent achieves higher density through increased vertical integration rather than more complex planar scaling. This approach uses established fabrication processes adapted for 3D structures, avoiding the exponentially increasing costs associated with continuing planar process scaling at sub-10nm nodes.
3Reliability
If the gate dielectric layer thickness is reduced to improve transistor performance, then device performance is improved, but parasitic capacitance increases
Solution Approach 1:
The patent employs fully-depleted transistors where the channel is completely depleted of carriers, fundamentally changing the electrical characteristics. This allows for thinner gate dielectric layers to achieve better control and performance while the full depletion condition minimizes parasitic capacitance by eliminating free carriers in the channel that would otherwise contribute to capacitive effects.
Solution Approach 2:
The patent applies different gate dielectric thicknesses to different transistor types within the same device. First transistors have a first gate dielectric layer thickness optimized for their function, while second transistors have a thinner second gate dielectric layer optimized for memory cell operation. This local optimization allows each transistor type to achieve its performance goals with appropriate capacitance characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances memory density and reduces parasitic capacitance, improving device performance and integration while allowing for reduced device size by using fully-depleted transistors and strategic interconnects within the 3D memory device.
Implementation Method 1
The disposing of the first semiconductor layer includes wafer bonding, smart-cut and/or chemical vapor deposition.
Implementation Method 2
The disposing of the first semiconductor layer includes wafer bonding, smart-cut and/or chemical vapor deposition.
Implementation Method 3
The disposing of the first semiconductor layer includes wafer bonding, smart-cut and/or chemical vapor deposition.
Data Source
AI summary
The present disclosure provides a memory device having a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first set of peripheral circuits having a first transistor configured to operate with a first voltage, and a second set of peripheral circuits having a second transistor configured to operate with a second voltage lower than the first voltage. The second set of peripheral circuits are disposed over the first set of peripheral circuits. The second semiconductor structure includes memory cells coupled to the first semiconductor structure.