3D Memory Device Stacked CMOS Wafer Integration
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Solution Overview
Problem
The challenge in designing and fabricating 3D NAND memory devices is the shrinking CMOS area required for increasing 3D NAND layers, which complicates the integration of peripheral devices and increases costs, as the memory array size decreases under the same capacity.
Innovation Solution
A method and structure for forming a 3D memory device by stacking an array wafer with memory cells, a first CMOS wafer containing high-voltage string driver circuits, and a second CMOS wafer with low-voltage page buffer circuits, allowing for separate formation and integration of different voltage-level circuits in distinct semiconductor layers to reduce overall area and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of 3D NAND layers increases to improve memory density, then the memory array size decreases under the same capacity, but the CMOS area must also shrink which complicates integration and increases costs
Solution Approach 1:
The patent divides the CMOS peripheral devices into multiple separate areas (first CMOS area for string drivers, second CMOS area for page buffers) rather than consolidating them in a single location. This segmentation allows each CMOS area to be independently optimized and scaled, reducing integration complexity as memory density increases
Solution Approach 2:
The patent transitions from a two-dimensional planar layout to a three-dimensional stacked architecture where memory arrays and CMOS peripherals are arranged in different vertical layers. This dimensional change allows the memory array and CMOS areas to coexist without competing for the same lateral space, enabling continued scaling of memory density while maintaining CMOS functionality
2Quantity of substance
If the memory array size is reduced to maintain the same capacity with more layers, then memory density improves, but the CMOS area must shrink which increases fabrication costs
Solution Approach 1:
By segmenting CMOS devices into separate first and second CMOS areas located at different positions, the patent enables independent fabrication and optimization of each CMOS region, reducing overall fabrication complexity and cost despite reduced CMOS area size
Solution Approach 2:
The patent assigns different functional characteristics to different CMOS areas - the first CMOS area contains string driver circuits requiring specific voltage levels and timing characteristics, while the second CMOS area contains page buffer circuits with different requirements. This local quality differentiation allows each region to be optimized for its specific function, improving overall manufacturability
3Adaptability or versatility
If multiple CMOS areas are used to accommodate peripheral devices, then integration flexibility improves, but device design and fabrication become more challenging
Solution Approach 1:
The patent segments peripheral devices into functionally distinct first and second CMOS areas, where the first CMOS area handles string driver operations and the second CMOS area handles page buffer operations. This functional segmentation provides integration flexibility while reducing design complexity through modular architecture
Solution Approach 2:
The patent introduces intermediate connection structures (such as through-array vias and interconnect layers) that facilitate communication between the memory array, first CMOS area, and second CMOS area. These intermediaries enable the multiple CMOS areas to work together as a unified system, managing design complexity through standardized interface protocols
Data Source
AI summary
A method for forming a 3D memory device includes forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one string structure region for forming a string structure; forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one string structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region; forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region; and forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer stacked together.