3D Semiconductor Memory Vertical Electrode Integration
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Solution Overview
Problem
Conventional two-dimensional semiconductor devices face limitations in integration density due to the need for expensive equipment to form fine patterns, leading to a demand for three-dimensional semiconductor memory devices that can enhance integration density.
Innovation Solution
The development of three-dimensional semiconductor memory devices with a substrate featuring a cell array region and a connection region, including vertically stacked electrodes with stair step structures and isolation insulating patterns, which allow for increased integration density and efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar semiconductor devices are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked electrode structures. Multiple electrodes are stacked in the vertical direction (third direction) to increase integration density without requiring finer lateral patterning, thereby resolving the contradiction between integration density and device complexity.
2Manufacturing precision
If vertically stacked electrodes are implemented, then integration density increases, but electrical connection complexity increases
Solution Approach 1:
The electrode structure is segmented into multiple distinct electrodes stacked vertically, with each electrode having specific pad regions exposed at different heights. This segmentation allows independent electrical connection to each electrode through separate contact holes, simplifying the overall electrical connection process despite the increased integration density.
Solution Approach 2:
Different regions of the electrodes have different properties: pad regions are exposed at specific heights for electrical connection, while other regions are covered by adjacent electrodes. This local differentiation enables efficient electrical connections only where needed, reducing overall connection complexity.
3Manufacturing precision
If fine patterns are formed in 2D devices, then integration density improves, but manufacturing cost increases
Solution Approach 1:
Instead of achieving higher integration density through finer lateral patterning in the two-dimensional plane, the patent uses vertical stacking of electrodes in the third dimension. This approach achieves high integration density without requiring extremely fine lateral patterns, thereby avoiding the need for expensive patterning equipment.
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region. Widths in the second direction of the pad portions may be different from widths in the second direction of the respective electrode portions.