3D Semiconductor Memory With Stacked Electrodes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing cost per bit for three-dimensional semiconductor memory devices is high due to the limitations of current manufacturing technologies, which hinder the mass production of these devices and their integration density improvement compared to two-dimensional devices.
Innovation Solution
A three-dimensional semiconductor device design featuring vertically stacked electrodes, active patterns, and information storage elements, with specific electrical connections and interconnection lines, allowing for increased data storage per unit area and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor memory devices are manufactured using current manufacturing technologies, then data storage capacity per unit area is increased, but manufacturing cost per bit becomes high
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple electrode groups (first electrode group, second electrode group, third electrode group) are stacked in the vertical direction, with active patterns extending through multiple layers. This dimensional change enables significantly increased storage capacity per unit area by utilizing the vertical space above the substrate rather than only the planar surface area.
Solution Approach 2:
The memory device is segmented into multiple electrode groups (first, second, third electrode groups) stacked vertically, with each group containing multiple electrodes (first through fifth electrodes). The active patterns are also segmented into multiple regions (first active pattern region, second active pattern region, third active pattern region) corresponding to different storage cells. This segmentation allows independent addressing and control of individual memory cells within the three-dimensional structure.
2Manufacturing precision
If manufacturing apparatus precision is improved to create finer patterns for high integration density, then integration density increases, but manufacturing cost increases
Solution Approach 1:
Instead of relying solely on improving two-dimensional patterning precision through expensive manufacturing apparatus, the patent uses vertical stacking to achieve high integration density. The electrode groups and active patterns are formed in multiple vertical layers, allowing the device to achieve high density through the third dimension rather than requiring extremely precise lateral patterning at each layer.
3Reliability
If two electrodes positioned at opposite sides of an active pattern are electrically separated, then storage reliability is improved, but device complexity increases
Solution Approach 1:
The electrode structure is segmented into odd-numbered electrode groups (first, third electrode groups) and even-numbered electrode groups (second electrode group). Electrodes within odd groups are electrically connected to form one potential, while electrodes within even groups are connected to form another potential. This segmentation provides electrical isolation between adjacent storage cells, improving reliability by preventing unintended coupling, while the systematic connection pattern manages device complexity through regularity.
Solution Approach 2:
Electrodes within the same electrode group are maintained at the same electrical potential through internal connections. For example, the first and third electrodes in the first electrode group are connected to form an equipotential region, and the second electrode in the second electrode group forms another equipotential region. This equipotential design simplifies voltage control and ensures uniform electrical characteristics across the three-dimensional structure.
Data Source
AI summary
A three-dimensional semiconductor device comprises active patterns arranged two-dimensionally on a substrate, electrodes arranged three-dimensionally between the active patterns, and memory regions arranged three-dimensionally at intersecting points defined by the active patterns and the electrodes. Each of the active patterns is used as a common current path for an electrical connection to two different memory regions that are formed at the same height from the substrate.