3D Nonvolatile Memory Stacked Gate Transistors
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Solution Overview
Problem
As the demand for higher bit densities and lower costs in flash memory storage continues, existing lithography downscaling technologies face scaling limits and increasing patterning difficulties, making it challenging to achieve both increased bit density and reduced costs.
Innovation Solution
A nonvolatile semiconductor memory device with a three-dimensional configuration, featuring a stacked body of alternating electrode and insulating layers, selection gate electrode layers, and a semiconductor member with a charge storage film, allowing for multiple selection transistors with different threshold potentials and improved cut-off characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If lithography downscaling technology is pursued to increase bit density, then bit density is improved, but manufacturing precision and patterning difficulty worsen due to scaling limits
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking configuration. Multiple electrode layers (first electrode layers 401D-404D, second electrode layers 401S-404S) are stacked vertically to form memory cells in the third dimension, thereby increasing bit density without requiring further lithography downscaling. This dimensional change allows continued scaling of storage capacity while avoiding the manufacturing precision limitations of conventional planar approaches.
2Quantity of substance
If multiple selection gate electrode layers are stacked to increase bit density, then bit density is improved, but device complexity increases
Solution Approach 1:
The selection gate structure is segmented into multiple discrete electrode layers (first selection gate electrode layers 451D-453D and second selection gate electrode layers 451S-453S) stacked vertically. Each layer can be independently controlled with separate potential application, allowing selective addressing of specific memory strings. This segmentation enables complex three-dimensional memory organization while maintaining manageable structural complexity through modular layering and independent control of each gate layer.
Solution Approach 2:
The stacked electrode layers serve multiple functions: they act as control gates for selecting memory strings, provide charge storage regions, and enable three-dimensional memory cell formation. The first and second electrode layers can function as both selection gates and charge trapping regions depending on the operational mode, reducing the need for separate dedicated structures and thereby managing device complexity while achieving high bit density.
3Reliability
If selection transistors with different threshold potentials are implemented, then misprogramming is suppressed, but ease of manufacture worsens due to additional processing steps
Solution Approach 1:
Different threshold potentials are implemented in different selection transistors located at different positions within the memory device. Specifically, selection transistors associated with first electrode layers have different threshold characteristics than those associated with second electrode layers. This local differentiation of electrical properties allows the system to distinguish between selected and unselected memory strings during read/write operations, suppressing misprogramming while managing fabrication complexity through spatially differentiated transistor characteristics.
Data Source
AI summary
According to one embodiment, a memory device, includes: a stacked body including first electrode layers stacked alternately with first insulating layers; a selection gate stacked body including selection gate electrode layers stacked alternately with second insulating layers in a stacking direction of the stacked body; a semiconductor member provided inside the stacked body and the selection gate stacked body, the semiconductor member extending in the stacking direction; a memory film provided between the semiconductor member and each of the f first electrode layers; and a gate insulator film provided between the semiconductor member and each of the selection gate electrode layers. Selection transistors are provided on the stacked body, the plurality of selection transistors included the selection gate electrode layers, the gate insulator film, and the semiconductor member, at least two of the selection transistors have mutually different threshold potentials.