3D Memory Stacked Layers Preventing Leakage Current
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Solution Overview
Problem
Existing 3-dimensional non-volatile memory devices face challenges in replacing sacrificial layers with conductive layers, leading to issues like yield reduction, degradation of erase characteristics, and leakage current due to exposed conductive material during the manufacturing process.
Innovation Solution
A semiconductor device and manufacturing method involving alternately stacked conductive and insulating layers, with slit insulating layers and air gaps to prevent exposure of metal residues, ensuring stable structure and process yield by sealing metal residues within the insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sacrificial layers are replaced with conductive layers in existing 3-dimensional memory devices, then memory cell stacking is achieved, but conductive material remains in undesired areas causing chemical reactions and leakage current
Solution Approach 1:
The patent extracts and removes the sacrificial layers completely after forming the conductive layers, eliminating the source of leakage current and chemical reactions. The sacrificial layers are used only temporarily during manufacturing and then fully removed to prevent any remaining material from causing reliability issues.
Solution Approach 2:
The patent introduces insulating layers as intermediary materials between the conductive layers and the substrate/other structures. These insulating layers prevent direct contact between conductive materials that could cause leakage current and chemical reactions, while still allowing the stacked memory cell structure to function.
2Productivity
If sacrificial layers are replaced with conductive layers, then stacked memory cells are formed, but the replacement process is difficult and yield is reduced
Solution Approach 1:
The patent performs preliminary actions by forming the sacrificial layers and insulating layers in a specific alternating sequence before forming the conductive layers. This preliminary structuring simplifies the subsequent replacement process and makes the manufacturing more straightforward and yield-friendly.
Solution Approach 2:
The patent employs a process where sacrificial layers are discarded (removed) after serving their temporary purpose of defining the structure during manufacturing. The removal process is designed to be straightforward, allowing efficient recovery of the final stacked memory cell structure without complex steps.
3Device complexity
If conductive material remains exposed after replacement, then manufacturing complexity is reduced, but chemical reactions occur and erase characteristics degrade
Solution Approach 1:
The patent introduces insulating layers as intermediary materials that completely cover and isolate any remaining conductive material. This intermediary layer prevents direct exposure of conductive material to chemicals during subsequent manufacturing steps, eliminating chemical reactions while maintaining a relatively simple manufacturing process.
Solution Approach 2:
The insulating layers create an inert environment around any remaining conductive material, preventing it from reacting with chemical substances during the manufacturing process. This protective barrier approach maintains manufacturing simplicity while eliminating the harmful chemical reactions.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device may include stacks including conductive layers and insulating layers. The conductive layers and insulating layers may be alternately stacked. The semiconductor device may include semiconductor patterns passing through the stacks. The semiconductor device may include plug patterns located on the semiconductor patterns and protruding compared to the stacks. The semiconductor device may include insulating patterns located on the stacks and the plug patterns and each including an edge area having a height at a level lower than a central area. The semiconductor device may include slit insulating layers located between the stacks and between the insulating patterns.