3D Semiconductor Memory Device Vertical Integration
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Solution Overview
Problem
The integration density and reliability of traditional two-dimensional semiconductor memory devices are limited by their available planar area, which restricts cost savings and performance.
Innovation Solution
A three-dimensional (3D) semiconductor memory device design featuring vertically stacked electrode structures, semiconductor pillars, and distinct threshold voltage string selection transistor units, allowing for improved integration density and selective control of electrical connections between bit lines and cell strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory device design is used, then manufacturing process is simpler, but integration density is limited by available planar area
Solution Approach 1:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional vertical structure. Multiple electrode structures (first and second electrode structures) are stacked vertically with semiconductor pillars extending through them, creating a multi-layer architecture that dramatically increases integration density by utilizing the vertical dimension rather than only horizontal plane area.
2Reliability
If traditional string selection transistor units are used, then device structure is simpler, but reliability is reduced due to short channel effects
Solution Approach 1:
The string selection function is divided into separate transistor units with different threshold voltages (first string selection transistor units and second string selection transistor units). This segmentation allows independent optimization of each transistor's characteristics, enabling better control over short channel effects and improved reliability while maintaining manageable structural complexity through modular design.
3Quantity of substance
If vertically stacked electrode structures are implemented, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent combines multiple electrode structures and semiconductor pillars into an integrated three-dimensional assembly where components share common structural elements. The semiconductor pillars extend through multiple electrode structures, creating a unified architecture that reduces the number of separate alignment operations required compared to fully discrete stacked structures, thereby mitigating manufacturing precision challenges while maintaining high integration density.
Data Source
AI summary
A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.