3D Memory Structure With Vertically Stacked Read Transistor
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Solution Overview
Problem
Existing memory structures face challenges in reducing size due to the direct formation of both transistors on the substrate, limiting the ability to minimize the overall size of the memory structure.
Innovation Solution
The memory structure is designed with one transistor formed directly on the substrate and the other transistor vertically offset, reducing the footprint by incorporating the read transistor within an interconnect structure, while maintaining sufficient write current for precise control of storage elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If both transistors are formed directly on the substrate, then the memory structure can be manufactured using conventional processes, but the overall size of the memory structure increases
Solution Approach 1:
The patent transitions from a planar two-transistor configuration to a three-dimensional stacked architecture where the read transistor is positioned vertically above the substrate in an interconnect structure, while the write transistor remains on the substrate. This dimensional change reduces the lateral footprint of the memory structure while maintaining functionality.
Solution Approach 2:
The memory structure is segmented into two distinct transistor implementations: the write transistor formed directly on the substrate using conventional processes, and the read transistor formed within the interconnect structure above the substrate. This segmentation allows each transistor to be optimized for its specific function while reducing overall area.
2Area of stationary object
If the read transistor is incorporated within the interconnect structure, then the memory structure size is reduced, but the structural complexity increases
Solution Approach 1:
The interconnect structure serves multiple functions: it provides electrical connections between memory cells and simultaneously houses the read transistor. This multi-functionality reduces the need for separate structures, thereby reducing overall area while managing complexity through functional integration.
3Area of stationary object
If the read transistor is vertically offset from the substrate, then the memory structure footprint is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The interconnect structure and read transistor are formed in advance during the manufacturing process, establishing precise alignment references before the write transistor and storage elements are formed. This preliminary action ensures that subsequent layers can be aligned to the established structure, reducing the overall precision burden.
Data Source
AI summary
A method of making a semiconductor device includes forming a write transistor partially in a substrate. The method further includes forming an interconnect structure over the substrate. The method further includes forming a read transistor in the interconnect structure, wherein the read transistor is physically separated from the substrate. The method further includes forming at least one storage element electrically connected to each of the write transistor and the read transistor, wherein forming the at least one storage element comprises forming the at least one storage element between the write transistor and the read transistor in a direction perpendicular to a top surface of the substrate.