3D Memory Device Stacked Word Lines
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Solution Overview
Problem
Conventional planar semiconductor device fabrication techniques become challenging and costly as feature sizes approach a lower limit, necessitating a more efficient method for forming high-density memory devices.
Innovation Solution
A 3D memory device architecture is developed, featuring a doped semiconductor layer with interleaved conductive and dielectric layers, including word lines and select gate lines made of the same material, and a channel structure extending through the stack, allowing for direct contact and improved interconnects, along with a method for forming these structures through sacrificial layer removal and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar semiconductor device fabrication techniques are used to scale devices to smaller sizes, then device density is improved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent transitions from planar 2D device architecture to three-dimensional stacked architecture. Multiple semiconductor layers are stacked vertically with interconnect structures connecting different layers, enabling continued density improvement by utilizing the vertical dimension rather than continuing to scale lateral dimensions where manufacturing complexity becomes prohibitive
2Quantity of substance
If feature sizes are reduced to increase device density, then memory capacity is improved, but fabrication precision requirements become more stringent and costly
Solution Approach 1:
Instead of continuing to reduce feature sizes in the lateral plane which demands ever-increasing fabrication precision, the patent stacks multiple layers vertically where each layer can be formed with relaxed precision requirements, achieving memory capacity improvement through increased layer count rather than smaller features
3Device complexity
If conventional planar processes are used, then device simplicity is maintained, but device footprint and power consumption increase
Solution Approach 1:
The patent consolidates multiple functional layers into a compact vertical stack, reducing the lateral footprint significantly compared to planar arrangements. The stacked configuration maintains relative structural simplicity while achieving higher density by utilizing vertical space rather than expanding laterally
Data Source
AI summary
A three-dimensional (3D) memory device includes a doped semiconductor layer, a stack structure, and a channel structure. The stack structure includes interleaved conductive layers and dielectric layers formed on the doped semiconductor layer. The conductive layers include a plurality of word lines, and a drain select gate line. The channel structure extends through the stack structure along a first direction and is in contact with the doped semiconductor layer. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The drain select gate line is in direct contact with the semiconductor channel, each of the plurality of word lines is in direct contact with the memory film, and the drain select gate line and the plurality of word lines include a same material.