3D Vertical Memory Stacking With Buried Dielectric Connections
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited due to the high cost and complexity of fine pattern formation, necessitating the development of three-dimensional semiconductor memory devices to enhance electrical characteristics and reliability.
Innovation Solution
A semiconductor device with a vertical structure comprising stacked gate electrodes, a channel structure, and a buried pattern, including dielectric materials, to facilitate enhanced integration and connectivity between peripheral circuit transistors and memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation technology to increase degree of integration, then data storage capacity increases, but manufacturing cost increases and device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple gate electrodes are stacked vertically with channel structures passing through them, enabling data storage capacity expansion along the vertical dimension rather than requiring increasingly complex fine pattern formation in the planar direction.
2Quantity of substance
If two-dimensional semiconductor devices use fine pattern formation technology to increase degree of integration, then data storage capacity increases, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple gate electrodes are stacked vertically with channel structures passing through them, enabling data storage capacity expansion along the vertical dimension rather than requiring increasingly complex fine pattern formation in the planar direction.
3Quantity of substance
If three-dimensional memory cells are stacked vertically to increase degree of integration, then data storage capacity increases, but electrical connection complexity increases
Solution Approach 1:
The patent divides the three-dimensional memory structure into repeating modular units, where each memory cell consists of stacked gate electrodes with channel structures passing through them. This segmentation allows standardized fabrication processes to be applied repeatedly, simplifying the manufacturing of complex electrical connections compared to custom-routed three-dimensional interconnects.
Solution Approach 2:
The channel structures serve multiple functions: they provide the conductive path for memory operation and simultaneously act as spacers defining the vertical spacing between gate electrodes. This multi-functionality reduces the number of separate components and simplifies the overall electrical connection architecture.
Data Source
AI summary
A semiconductor device includes a first substrate, a plurality of gate electrodes stacked on an upper surface of the first substrate in a vertical direction, the plurality of gate electrodes being apart from one another in the vertical direction, a channel structure passing through the plurality of gate electrodes, a second substrate disposed between the first substrate and a lowermost gate electrode of the plurality of gate electrodes, the second substrate including a first surface and a second surface opposite to the first surface, a buried pattern passing through the second substrate, and a vertical structure passing through the buried pattern, wherein the buried pattern includes a dielectric material.