3D Memory Stacking Structure With Shorter Interconnect Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor device scaling is to achieve improved quality, yield, performance, and reliability while reducing complexity and power consumption, which is hindered by the limitations in stacking structures and interconnects.
Innovation Solution
The semiconductor device incorporates a bottom die with stacked structures, including a first controller die and storage dies configured as a floating array, and a second controller die with storage dies featuring an insulator-conductor-insulator structure, integrated through interconnect units, reducing dimensions and electrical paths to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional stacking structures are used, then device functionality is achieved, but device dimensions and power consumption increase
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking architecture, organizing controller dies and storage dies in vertical layers. This dimensional change enables higher integration density while reducing the lateral footprint of the device, directly addressing the contradiction between compact dimensions and functional reliability.
Solution Approach 2:
The patent implements a nested stacking structure where multiple storage dies are positioned on top of controller dies, which themselves are positioned on the bottom die. This nested arrangement allows multiple functional layers to be integrated within a compact vertical space, reducing overall device volume while maintaining complex functionality through hierarchical organization.
2Use of energy by moving object
If stacking structures with multiple interconnect units are used, then device functionality is achieved, but power consumption increases due to longer electrical paths
Solution Approach 1:
The patent applies different interconnect configurations to different regions of the stacking structure. Through-substrate vias are strategically positioned to create optimized electrical paths for specific signal types, while other interconnect units handle different functions. This localized optimization reduces overall power consumption by minimizing electrical path lengths for critical signals while managing structural complexity through regional differentiation.
Solution Approach 2:
The patent introduces intermediate controller dies that act as mediators between storage dies and the bottom die. These intermediary layers provide local control and signal routing, reducing the need for long direct electrical paths through the entire stack. The intermediary controllers manage data flow and power distribution locally, thereby reducing overall power consumption while organizing the complex stacking structure into manageable functional modules.
Data Source
AI summary
The present application discloses a semiconductor device with stacking structures. The semiconductor device includes a bottom die; a first stacking structure including a first controller die positioned on the bottom die, and a plurality of first storage dies stacked on the first controller die; and a second stacking structure including a second controller die positioned on the bottom die, and a plurality of second storage dies stacked on the second controller die. The plurality of first storage dies respectively include a plurality of first storage units configured as a floating array. The plurality of second storage dies include a plurality of second storage units respectively including an insulator-conductor-insulator structure.