3D Vertical Transistor Memory Stacking Beyond Planar Scaling Limits
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Solution Overview
Problem
Planar memory cells face challenges in scaling due to increased complexity and cost as feature sizes approach a lower limit, limiting memory density.
Innovation Solution
Implementing a 3D memory architecture with vertical transistors and peripheral circuits formed on separate semiconductor structures, bonded face-to-face, allowing for increased memory cell density and reduced chip size through vertical integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled to smaller sizes by improving process technology, then memory density is improved, but process complexity and fabrication cost increase significantly
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional (3D) stacked architecture. Multiple memory cell arrays are formed on separate semiconductor structures (wafer 102, wafer 104, wafer 106) and bonded together vertically, enabling memory density scaling by utilizing the vertical dimension rather than continuing to scale lateral dimensions, thereby avoiding the exponential increase in process complexity associated with further planar scaling.
Solution Approach 2:
The memory device is divided into multiple separate semiconductor structures (first semiconductor structure 102, second semiconductor structure 104, third semiconductor structure 106), each containing memory cell arrays. These segmented structures are fabricated independently and then bonded together, allowing parallel fabrication processes and reducing the complexity of fabricating a single large-scale integrated structure.
2Quantity of substance
If feature sizes of memory cells approach a lower limit, then memory density approaches an upper limit, but planar process techniques become challenging and costly
Solution Approach 1:
By stacking memory cell arrays vertically across multiple semiconductor structures bonded at bonding interfaces, the patent achieves high memory density without requiring further reduction of lateral feature sizes. This vertical integration approach maintains fabrication ease by using established planar processes for each individual structure while achieving overall high density through 3D integration.
3Quantity of substance
If 3D memory architecture is implemented with vertical transistors and bonded semiconductor structures, then memory cell density increases and chip size reduces, but interconnect structures become more complex
Solution Approach 1:
The interconnect structure is segmented into multiple independent interconnect layers formed on each semiconductor structure (interconnect layer 122 on wafer 102, interconnect layer 124 on wafer 104, interconnect layer 126 on wafer 106). These segmented interconnect structures simplify the design and fabrication of each individual layer while achieving complex 3D interconnection through vertical stacking and bonding interfaces.
Data Source
AI summary
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes a first array of memory cells. The third semiconductor structure includes a second array of memory cells. Each of the memory cells of the first and second arrays includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The first array of memory cells is coupled to the peripheral circuit across the first bonding interface. The second array of memory cells is coupled to the peripheral circuit across the first bonding interface and the second bonding interfaces.