3D Semiconductor Memory Stacking via Segmented Lithography
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Solution Overview
Problem
Current 3D stacked semiconductor chip technologies face challenges in achieving high-density connections between layers due to misalignment issues and the need for high-temperature processing, which damages lower wiring layers and limits connectivity.
Innovation Solution
The development of methods for constructing 3D memory devices with single crystal transistors and layers using lithographic and etch steps, aligned with alignment marks, to form high-density memory cells and transistors, and bonding oxide-to-oxide to achieve reliable and high-density connections without degrading existing layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature processing (>700°C) is used to construct transistor layers, then transistor performance and density improve, but lower wiring layers are damaged
Solution Approach 1:
The patent divides the 3D stacked chip into separate processing stages: bottom transistor layer and wiring layers are constructed first, then the top transistor layer is constructed separately at low temperature, and finally the layers are bonded together. This segmentation allows each layer to be processed under optimal conditions without damaging other layers.
Solution Approach 2:
The bottom transistor layer and wiring layers are constructed in advance before the top transistor layer is added. This preliminary construction allows the sensitive wiring layers to be established first, protecting them from subsequent high-temperature processing when the top transistor layer is formed.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay decreases, but alignment precision and connectivity density are limited
Solution Approach 1:
The patent replaces traditional mechanical alignment methods with lithographic alignment techniques. Alignment marks are formed on both the bottom and top layers, and lithographic steps are used to precisely pattern features relative to these marks, achieving sub-40nm alignment accuracy that overcomes limitations of mechanical wafer bonding alignment.
3Reliability
If contact size is increased to improve alignment tolerance, then alignment robustness improves, but connectivity density decreases
Solution Approach 1:
The patent uses lithographic patterning (an optical field-based process) instead of mechanical contact methods to define alignment features. This allows for precise, small-sized alignment marks and contact regions that maintain alignment robustness while enabling high connectivity density, as the optical process can accurately pattern features at the desired scale without requiring large physical tolerances.
Data Source
AI summary
A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, and where the additional processing steps include depositing a gate electrode simultaneously for the second and third transistors.