3D Memory Integration via Vertical Stacking and Tunnel Oxidation
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Solution Overview
Problem
The integration density of traditional two-dimensional memory semiconductor devices is limited by the high cost of equipment required for forming fine patterns, and there is a need for techniques that can enhance integration density beyond these limitations.
Innovation Solution
A method of fabricating a semiconductor device with a three-dimensional structure, involving the formation of a charge storage layer, a tunnel insulating layer, and multiple semiconductor layers, where the tunnel insulating layer is formed through heat treatment processes such as oxidation or nitriding, and the use of alternating conductive and insulating layers on a substrate to create a reverse gate stack structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hyper-fine patterns are formed using traditional two-dimensional memory semiconductor devices, then integration degree is improved, but manufacturing cost increases due to high-priced equipment requirements
Solution Approach 1:
The patent transitions from traditional two-dimensional planar memory cells to three-dimensional vertical memory structures. By stacking multiple memory cells vertically and forming gate electrodes in the vertical direction, the invention achieves higher integration density without requiring hyper-fine lateral patterning, thus avoiding the need for expensive equipment while improving manufacturing feasibility
Solution Approach 2:
The memory device is divided into multiple stacked memory cells, each with its own charge storage layer and tunnel insulating layer. This segmentation allows independent formation of each cell layer through sequential deposition and heat treatment processes, enabling cost-effective manufacturing while achieving high integration through vertical stacking
2Ease of manufacture
If traditional two-dimensional memory structures are used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The invention employs vertical stacking of memory cells along the z-axis, transforming the two-dimensional planar structure into a three-dimensional architecture. This dimensional change enables significantly higher integration density while maintaining manufacturing simplicity through sequential layer deposition and heat treatment processes that form tunnel insulating layers on charge storage layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for increased integration density in semiconductor devices, overcoming the limitations of two-dimensional structures by enabling the formation of high-density, cost-effective three-dimensional memory cells with improved performance.
Implementation Method 1
The heat treating the charge storage layer may include one of an oxidation process or a nitriding process. The oxidation process may include at least one of a radical oxidation and wet oxidation.
Implementation Method 2
The heat treating the charge storage layer may include one of an oxidation process or a nitriding process. The nitriding process may include at least one of a plasma nitration and thermal nitration.
Data Source
AI summary
A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer.