3D Memory Cell Stacks With Overlying Multiplexers for Dense Arrays
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the horizontal footprint and improving control logic device configurations, which are limited by processing conditions and complex architectures.
Innovation Solution
The formation of vertical stacks of memory cells with conductive pillar structures and multiplexers, along with transistors, allows for increased density and improved control operations by vertically integrating memory cells and routing structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If control logic devices are formed within a base control logic structure underlying the memory array, then control operations can be performed, but the processing conditions limit the configurations and performance of the control logic devices
Solution Approach 1:
The patent divides the control logic devices into separate discrete structures that are formed independently from the memory array. This segmentation allows the control logic devices to be manufactured under optimized conditions separate from the memory array processing, thereby improving configurability and performance without being constrained by the base control logic structure's processing limitations.
Solution Approach 2:
The patent transitions control logic devices from a planar base structure to a three-dimensional architecture where control logic devices are positioned at different vertical levels and orientations. This dimensional change enables more flexible configurations and improved performance while maintaining compatibility with standard processing conditions.
2Productivity
If the quantity and complexity of control logic devices increase to handle denser memory arrays, then control operations improve, but the control logic devices consume more real estate, reducing memory density
Solution Approach 1:
The patent utilizes three-dimensional stacking to position control logic devices vertically above and around the memory array rather than spreading them out in the planar domain. This vertical integration dramatically reduces the horizontal footprint of control logic devices, allowing higher memory density while maintaining sufficient control logic capacity for dense memory arrays.
Solution Approach 2:
The patent embeds control logic devices within and around the memory array structure itself, nesting control functions within the same vertical space occupied by memory cells. This nested arrangement allows control logic devices to share the same real estate as memory structures, thereby improving control capability without sacrificing memory density.
3Quantity of substance
If the separation distance between neighboring features is reduced to increase integration density, then feature density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms memory structures and control logic devices as separate segmented units with standardized interface structures. This segmentation approach allows each unit to be manufactured independently with relaxed precision requirements, then assembled into high-density arrays through self-aligned processes that maintain consistent separation distances without requiring extreme manufacturing precision.
Data Source
AI summary
A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.