3D Memory Cell Stacks With Vertical Logic for Higher Density
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Solution Overview
Problem
Microelectronic device designs face challenges in increasing memory density and performance due to processing conditions and the complexity of control logic devices, which consume more space and hinder size reduction and performance improvements in memory devices.
Innovation Solution
The formation of vertical stacks of memory cells with access devices and storage devices, using conductive pillar structures and transistor structures that are vertically oriented over the memory cells, with protective liner materials to facilitate efficient electrical connections and minimize area consumption, allowing for improved memory device performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control logic devices are integrated within the base control logic structure underlying the memory array, then memory device functionality is achieved, but the control logic devices consume excessive real estate and hinder memory density improvement
Solution Approach 1:
The patent divides the microelectronic device into separate functional modules: memory cell arrays are formed independently on memory cell substrates, while control logic devices are formed separately on control logic substrates. This segmentation allows each module to be optimized independently, reducing the real estate consumption of control logic within the memory array and improving overall memory density.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture where memory cell substrates and control logic substrates are vertically stacked and interconnected. This dimensional change allows control logic devices to be positioned beneath or above memory arrays, freeing up horizontal space and increasing memory density without compromising control logic functionality.
2Reliability
If processing conditions are optimized for memory array formation over base control logic structure, then memory array performance is improved, but the configurations and performance of control logic devices are limited
Solution Approach 1:
By segmenting the device into separate memory and control logic modules formed on different substrates, each module can undergo optimized processing conditions tailored to its specific requirements. Memory arrays can be processed with conditions optimized for high-density storage, while control logic devices can be processed with conditions optimized for their specific transistor architectures and performance characteristics.
Solution Approach 2:
The patent employs preliminary action by forming control logic devices on separate substrates before final assembly. This allows control logic devices to be pre-optimized and tested independently, and then integrated with memory arrays through standardized interconnect structures, providing flexibility in controlling logic configuration without compromising memory array performance.
3Productivity
If the quantity and dimensions of control logic devices are increased to handle higher memory array complexity, then memory array functionality is enhanced, but the horizontal footprint of the memory device increases
Solution Approach 1:
The patent utilizes vertical stacking to position control logic substrates beneath or above memory cell substrates, connecting them through through-silicon vias and interconnect structures. This three-dimensional arrangement allows the memory device to achieve higher capacity through increased vertical integration rather than horizontal expansion, significantly reducing the horizontal footprint while maintaining or enhancing memory array functionality.
Solution Approach 2:
The patent implements a nested architecture where control logic devices are positioned within the vertical space occupied by memory arrays, with lower-level substrates supporting upper-level substrates. This nesting approach allows control logic to be embedded within the memory device structure rather than occupying separate horizontal space, reducing overall device footprint while maintaining high memory capacity.
Data Source
AI summary
A microelectronic device comprises vertical stacks of memory cells, each of the vertical stacks of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure in contact with the vertical stack of access devices. The microelectronic device further comprises transistor structures vertically overlying the vertical stacks of memory cells and comprising semiconductive material, and a protective liner material horizontally intervening between the semiconductive material and the conductive pillar structure of each of the vertical stacks of memory cells. Related methods are also described.