3D Memory Cell Array Layout for Faster Low-Capacitance Access
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration and miniaturization while maintaining efficient read and write speeds, particularly in stacked type semiconductor memory devices with perpendicular semiconductor pillars.
Innovation Solution
The semiconductor memory device employs a staggered arrangement of memory units with bit lines connected to memory cells, utilizing a U-shaped semiconductor layer as a channel body, allowing for twice the number of bit lines per memory unit and reducing parasitic capacitance, and incorporates shared select gate lines and differential sense amplifiers to enhance read speed and power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory units are arranged in a conventional aligned manner with bit lines connected to memory cells, then the circuit structure is simple, but the read/write speed is limited and parasitic capacitance is higher
Solution Approach 1:
The patent applies asymmetry by arranging memory units in a staggered configuration where adjacent memory units are displaced relative to each other in the row direction. This asymmetric arrangement allows bit lines to connect to memory cells in a pattern that doubles the effective connectivity, thereby doubling read/write speed while managing circuit complexity through systematic displacement rather than random complexity
Solution Approach 2:
The patent transitions from a conventional two-dimensional aligned arrangement to a staggered arrangement that effectively utilizes displacement in the row direction as an additional dimensional parameter. This dimensional change allows bit lines to serve multiple memory units more efficiently, doubling the number of bit lines per memory unit and increasing read/write speed without proportionally increasing circuit footprint
2Speed
If the number of bit lines per memory unit is increased to double read/write speed, then parasitic capacitance increases, but power consumption increases
Solution Approach 1:
The staggered asymmetric arrangement optimizes the distribution of bit lines across memory units, allowing twice the number of bit lines per memory unit to be effectively utilized. The systematic displacement pattern ensures that increased bit line connectivity doubles read/write speed while the shared select gate lines and differential sense amplifiers mitigate the power consumption increase from additional bit lines
3Quantity of substance
If circuit area is reduced to increase integration, then manufacturing precision requirements increase
Solution Approach 1:
The patent segments the memory array into multiple memory units with a staggered arrangement pattern. This segmentation allows the circuit footprint to be optimized for high integration density while maintaining manufacturability through systematic, repeatable displacement patterns that can be precisely controlled during fabrication
Solution Approach 2:
By utilizing displacement in the row direction as an additional dimensional parameter, the patent achieves high integration density without requiring excessive miniaturization in the conventional planar dimensions. This dimensional approach increases integration while maintaining manufacturing precision requirements at achievable levels
Data Source
AI summary
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.